Verification Of Synchronous And Asynchronous Memory Controller Based On SystemVerilog Language

With the development of integrated circuit technology, the size of chip is getting smaller, but its complexity and functionality are increasing, also along with the increasing market demand for chip production volume, the chip functional verification task is now facing enormous pressure and challenges. One of the most common problems now in the industry is the low success rate of the first tape-out and the longer chip development cycle. The reason of failure in the first tape-out is often the incomplete functional verification that causes the presence of functional defects. The long development cycle is caused mainly by increasing verification time. In order to solve these problems, how to build a highly efficient, highly reliable, and reusable verification environment as well as how to make verification better by analyzing the coverage and assertions is the focus of this thesis.Starting from the functional verification method of the basic learning agent, we will verify the function of EBIU (External Bus Interface Unit) module. Firstly, introduces the basic structure and function of EBIU, EBIU is actually an external memory interface, with the same function as memory interfaces. This thesis extracts the function test points after having a strong understanding of the design specifications about EBIU and set up a functional verification testbench for EBIU. Afterwards, thesis represents the process of EBIU functional verification in details, including the establishment of the verification testbench and the function and the implementation methods of each part of the verification testbench; It also describes the generation of random stimulus with constrain and the use of assertions; analyzes automatic matching of the data in verification testbench as well as the build of coverage statistical models; This thesis also discusses how to combinate the functional coverage and assertions with traditional verification methods effectivly; It demonstrates that the verification method that combines assertions and the functional coverage-driven is able to improve the observability during verification, to shorten the verification cycle and to ensure the thoroughness of verification. Finally, this thesis presents the result of coverage statistics of EBIU module, with functional coverage reaching 100%, code coverage reaching 94.65% and assertion coverage reaching 100%. After analyzing the reason that some code is uncovered, It is eventually proved that the verification testbench meets with our expected verification requirement.In this thesis, we build a verification testbench for EBIU module, which uses the randomized method that is based on coverage-driven and assertion. The verification testbench provides many advantages. For example, high efficiency and reusability. It completes functional verification for EBIU module with distinction. Practice has proved that the randomized method that is based on coverage-driven and assertion can greatly improve the efficiency of verification and ensure the completeness of verification, which has great significance for enhancing the quality of verification, shortening verification cycle and reducing the cost of verification.