Analysis Of Eye Diagram Based On High Speed Parallel Bus Of DDR4

Along with the development of the electronics industry, the application of high-speed serial bus is becoming more and more common. The position of high-speed parallel bus is still irreplaceable. In the design process of traditional slow parallel bus, we only need to make sure those interconnections and logical functions are good. But the speed of the single path of the parallel bus is as high as Gbps, and then, as a result, the problem of signal integrity in the high-speed parallel bus is becoming more and more obvious. Designers will have to make detailed evaluation on these issues which were caused by the high-speed interconnection. Commonly, there are two kinds of tools to evaluate the performance of interconnection: worst eye diagram and bit error rate eye diagram. However, in order to get these two kinds of eye diagram, people has to spend a lot of time on simulation, which is obviously a laborious and time-consuming way.In all kinds of parallel buses, the DDR SDRAM(Double Data Rate Synchronous Dynamic Random Access Memory) parallel bus is the fastest. So, the problem of signal integrity in DDR parallel bus is the most obvious. Based on DDR4 parallel bus, this paper proposes two kinds of algorithms to acquire the eye diagram. At first, some basic parameters of all previous dynasties DDR parallel bus are introduced, such as topology, clock frequency,interface logic level and so on. Then, the general problems of signal integrity arising in the design process of DDR parallel bus are presented, such as jitter, crosstalk and bit error rate.In terms of jitter, we introduce two main kinds of jitter: inter-symbol interference, and duty cycle distortion. After these, we introduce eye diagram as a useful tool to SI designer, and show the process of the worst eye diagram. At the same time, the relationship between bit error rate and the jitter of receiver and noise is deduced, and the origin of the bit error rate eye diagram is explained by using bathtub curve.Next, two kinds of algorithms which are the matrix method used to compute the worst eye diagram and the pulse response method used to compute the bit error rate eye diagram are introduced in detail. The matrix method which is the improvement of the multiple edge responses method is used to get the worst eye diagram. Through grouping multiple edge,superposition and getting the worst influence in every bit, the matrix method can be applied in nonlinear system. This method improves the accuracy of the worst eye diagram. Through the comparison of these two kinds of the worst eye diagram computed by the method presented in this paper and the traditional PDA algorithm, it is shown that the accuracy of matrix method is better than the traditional PDA algorithm.The single bit response is based on overlay linear system. The edge responses of the system simulated by Hspice are obtained firstly, and then the single bit response is compounded by the edge responses. Finally, bit error rate eye diagram is fast get through the superposition of different cursor position. The simulation software by using Matlab-GUI(Matlab Graphical User Interface) is also developed. These two algorithms above can be applied not only in DDR4 parallel bus but also in other high speed parallel buses.