Simulation Analysis Of Signal Integrity For DDR4 High-speed Concurrent Bus

With the development of Electronic Science and technology,the data transmission rate and working frequency of electronic equipment are constantly improving.DDR4 high-speed parallel bus is facing a more serious signal integrity problem.The simulation analysis of DDR4 high speed parallel bus is helpful to solve the problem of signal integrity of DDR4,provide reference for designers and promote the further popularization and development of DDR4.The main contents of this paper are as follows:1.ADS2016 software is used to simulate the problem of reflection and crosstalk in the signal integrity of high speed circuits.The simulation validates the four transmission line matching methods,four typical discontinuous reflection and crosstalk,which lays the foundation for the subsequent chapters.2.By reading the design standard of DDR4,the main design indexes such as eye diagram are extracted.And verify the DDR4 high-speed parallel bus simulation circuit and IBIS model.3.Use Sigrity2017 to simulate DDR4 high-speed parallel bus circuit.Through the simulation,select the ODT,verify the DBI function in the DDR4 high speed parallel bus and the eye pattern when the data transmission rate is different.4.The simulation results of DDR4 high-speed parallel bus circuit are compared with the DDR4 design indexes to determine whether the design requirements of DDR4 are satisfied.Through the above research,the data transmission rate of the DDR4 high speed parallel bus simulation circuit in the "Write" and "Read" mode can reach 1.6Gpbs.When the data transmission rate is 1.6Gpbs,eye pattern and overshoot conditions meet the design requirements of DDR4.