High-speed Parallel Bus Interface Signal Integrity Analysis And Design

High-performance systems that incorporate features such as parallel processing or other complex functions, and operate at high clock speeds, place tough demands on the design of the boards that hold the circuits. Dealing with issues such as tight clock distribution and highspeed interfaces to meet forthcoming bandwidth-hungry applications are a few of the key challenges designers are facing today. With the increase of integrate circuit switch rate and PCB(Printed Circuit Board)density, Signal Integrity has become one of main problems in high-speed design. The problem caused by some factors such as parameters of devices and PCB, layout of devices on PCB and trace of high-speed signal, etc results in the unstable or even none operation of system. How to fully consider Signal Integrity and take effective measures has been pop task in PCB design trade. And the application of SI analysis in the system is an important topic too.Being the data path for each module in a system, bus has strong relation with the performance of the whole system. We have made a lot of research in this field before. We use signal integrity(SI) as an analysis tool for the bus design. The concept has been running through the whole process of digital circuit design.This paper introduces the problems of Signal Integrity in high-speed parallel bus interconnect design and the new design methodology. Discusses the correlative problems of time sequence, reflection, crosstalk and ground rebound noise. Simulates the corresponding waveform in virtue of Cadence core EDA software SpecctraQuest. On the base of the discussion above, I finished the actual project that is Visual Telephone design. The PCB board has steady performance, attain to the success of making board for the first time, which shortens the research period, saves cost and proves that the method of Signal Integrity analysis is important to high-speed interconnect design.