A Design Of The New Successive Approximation Register-controlled Delay Locked Loop

With the continuous development of CMOS process technology, chip integration gradually increasing, chip area also become smaller with it, many of the functional modules are integrated on a chip, and the operating frequency to Gigahertz. In this case, clock skew has become the important problem in the digital systems, so delay-locked ring have been widely used to solve serious problems caused by clock skew.Delay lock ring is divided into all-digital, all-analog, mixed and mixture of digital and analog, the three types of locking ring has its own advantages and drawbacks, Which digital delay locked loop have the strong ability to resist process, temperature, voltage (PTV) and other outside factors. The advantages of digital delay locked loop is that it have ability to resistant to technology, temperature and voltage (PTV), and fast locking speed, easy to integrate, relative to all-analog and mixture of digital and analog locked loop, for low-voltage, low-power design using all-digital delay locked loop is the best choice, but it has a disadvantage is larger phase difference. Analog delay-locked ring locking between input signal and output signal phase difference is smaller, because it uses adjustable voltage-controlled delay line, because of analog delay locked loop using full-custom design, so its area and power consumption is relatively small, but it weak to resist the process, temperature and voltage (PTV). Mixed delay locked loop combines the advantages of digital delay locked loop and analog delay locked loop, but the digital signal will be interference to analog signal, so the mixed delay locked loop is not easy to achieve.All-digital delay locked loop applies to low-voltage, low-power design, so it has been widely used. All-digital delay locked loop is divided into a register-based delay-locked loop, the counter-type delay-locked loop, successive approximation register-based delay locked loop, in which successive approximation register-based digital delay locked loop locking speed faster. Traditional all-digital successive approximation register-based delay locked loop require lock time greater than the theoretical value, harmonic locking and dead locks, etc. In this paper, the design of the new all-digital successive approximation register-based CNC delay line that is consisted by the reusable delay unit,all the delay unit is reset before allowing the reference clock into the delay line, due to a delay unit is reset after the delay line does not exist any interference signal, sothe feedback clock signal can timely and properly reflect through the delay line after the clock signal, that is say the delay line what kind of impact to clock signal, since this can make the successive approximation register controller’s operating frequency is consistent with operating frequency of the input clock, in addition can accelerate the locking speed of the lock ring and then get to the theoretical value and can eliminate the harmonic lock; the new all-digital successive approximation register-based delay-locked loop increase the restart circuit to solve deadlock problems.This article uses electronic automation tools VCS, DC and ICC as a platform of design, SMIC CMOS0.18um1P6M process, using SPICE simulator HSIM tool to simulate the new all-digital successive approximation register-based delay-locked transistor-level circuit, according to simulate results prove the correctness of the improved tradition delay locked loop.