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Design Of Low Noise Amplifier In Navigation Receiver

Posted on:2016-12-06Degree:MasterType:Thesis
Country:ChinaCandidate:X P MaFull Text:PDF
GTID:2348330488472977Subject:Integrated circuit system design
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In recent years, the satellite navigation industry has developed rapidly, as an important part of the satellite navigation and positioning system, RF receiver becomes the focus of the study design. As the first active part of the RF receiver, the function of the low noise amplifier(LNA) is amplifying the faint signal which accepts from air by the antenna. It can reduce the noise jamming, so as to demodulate right information for the system. Its noise figure and gain are very important to the RF receiver. So it is very import to design a low noise amplifier with good performance.This paper designed two kinds of structures of LNA which one is an inductively degenerated common source amplifier and another is a cascade CG applied to the national navigation system based on TSMC 0.18 um CMOS process,completed the layout and post-layout simulation.Firstly, performance indexes of LNA are introduced and the two kinds of LNA proposed are implemented after some research on noise and topologies which are often used in the design of LNA. To make the LNA have good noise performance, this paper introduced two kinds of noise optimization techniques, which one use cross-coupling capacitance to increase trans-conductance and reduce the noise, another is computing the best gate width under power constraint. And then analyzed the advantages of the structure of LNA proposed and stimulated the two kinds of LNA by ADS and got the good simulation results. According to the practical application and consideration of mismatch between single-end antenna and differential LNA, a LC BALUN was designed and simulated. Finally, this paper completed the layout and post-simulation. After simulation parameters were compared with the previous simulation, and then analyzed the reasons for the change.The proposed LNA were designed based on TSMC 0.18 um CMOS process. Schematic, layout, and post-layout simulation were done by ADS and Cadence. The previous simulation results show that, at 1.561 GHz, the Cascode CG LNA achieves a NF of 2.259 d B which is half the traditional CG LNA, a gain of 18.908 d B, the reverse transmitted coefficient of-40.694 d B,the 1d B compression point of-26.64 d Bm, and good performance of sensitivity and input-output matching. The Cascode CS LNA provides again of 25.797 d B with a noise figure of 1.522 d B and the reverse transmitted coefficient of-40.934 d B while the power consumption is 10.26 mw which is much smaller than CG LNA. But value of 1d B compression point is not as good as the CG LNA.The layout of cascade CS LNA was completed, the area of the layout is 990um×406um,the pose-simulation results show that,at 1.561 GHz,the cascade CS LNA achieves a NF of 1.78 d B, a gain of 18.353 d B,the 1d B compression point of-24.1d Bm, the reverse transmitted coefficient of-46.44 d B, the gain and NF are not better than pre-simulation while the linearity and stability are better. The change of the performance of post-simulation is because of the parasitic and sensitivity of LNA to the change of device parameters.
Keywords/Search Tags:LNA, Noise Figure, Cascade, BALUN, CMOS
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