Cmos Rf Front-end Low Noise Amplifier Design

System on a chip (SOC) has become the main focus in the area of wireless communication. With the rapid development of mobile radio industry, low power consumption and high integration become key characteristics to reduce costs and weights and enhance the reliability of system. For a candidate of this requirement, CMOS technology draws attentions due to its mature application in base band uses.As the first block of the wireless receiver following antenna, the noise performance of LNA determines the noise performance of the entire system. Therefore, to improve the sensitivity of the receiver, the noise figure of the LNA (low noise amplifier) must be minimized and enough gain must be provided. This paper mainly focuses on the issues of RF CMOS LNA optimization.There are a lot of unsolved problems in RF CMOS LNA designing. In this paper, the performance of three main LNA topology; i.e. common gate structure, Cascode with source degeneration structure, and inverter structure, is discussed in detail, and the main research areas are:Firstly, common gate LNA is discussed detailed and one method to optimize the noise performance is put forward by increasing the trans_conductance of the common gate transistor.Secondly, noise performance of Cascode with source degeneration structure is analyzed systematically. After considering noise contribution from three main noise source of this structure, i.e. the input transistor, the cascade transistor, and the parasitical resistor of the planar inductor, and the methodologies are suggested to improve the noise performance .Lastly, the advantage and disadvantage of the inverter structure are discussed.