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FPGA-based SSD Controller Design And Implementation

Posted on:2015-01-06Degree:MasterType:Thesis
Country:ChinaCandidate:X P XuFull Text:PDF
GTID:2268330431958250Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
With the rapid development of computer technology, and CPU operation speedfaster and faster, the speed of traditional mechanical Hard-Disk driver’s read andwrite to a certain extent has hampered the development of the computer. To meet thedemand of The Times, faster read and faster write solid-state drives born. Now moremainstream solid-state drives storage medium is flash, compared with mechanicalhard-disk drivers in this structure can make the SSD has better shock and dropresistance, higher read and write speeds, lower power consumption, and theadvantages of no noise, large scope of work. But flash after many times to wipe, itsreliability will be reduced. And external data transfer speeds far greater than the flashmedia SSD speeds. In order to decrease the number of wipe for SSD flash and theintroduction of more cost-effective DDR3SDRAM as SSD cache.In this paper, the main content and specific research direction are given below.Through to DDR3SDRAM work mechanism and basic function of the structure ofthe analysis, combined with JESD79-3E specification, to conduct the thoroughresearch to the DDR3controller, the idea of top-down design, modular design thought,finally determine the using DDR3as SSD cache the overall design scheme of thecontroller. This paper uses Verilog HDL language design DDR3controller. Thedesign is complete command and control module is responsible for controlling readand write operations, initialization and other operations functions.Upon completion of the controller design, based on Altera’s Stratix IV in Quartus11.0development environment use Verilog HDL language to write the test bench.Using Modelsim6.6d simulation tools simulation each module of the controller, andgive the initialization, read and write sub-module RTL-level simulation results, thesequence diagram in Modelsim, verify the controller to normal initialized, read andwrite operations. And write the number of storage units for statistics, results showedthat the number of writes various locations close to the average, to achieve thepurpose of improving life.
Keywords/Search Tags:FPGA, SSD, DDR3, Controller
PDF Full Text Request
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