Research On SEU Fault Tolerance Among Sram-based FPGA Using Dynamic Reconfiguration

With the development of microelectronic technology and semiconductormanufacturing process, the sizes of transistors in integrated circuits have beenshrinked significantly, making them vulnerable to soft errors accordingly. Innowadays, SRAM-based FPGAs are widely applied in aerospace systems due totheir low development cost and power consumption. Unfortunately, numerous high-energy particles in the radiative environment may probably trigger Single EventUpsets (SEUs) among SRAM-based FPGAs, which finally results in system failures.Therefore, the technology of fault tolerance of FPGA needs to be highlighted withenormous attention.This dissertation is devoted to improve the reliability of SRAM-based FPGAsby means of fault tolerance technology. Firstly, the demonstration platform, whichuses the Virtex-5FPGA device as core, is designed and built to verify the feasibilityof fault tolerance approach and analyze fault tolerance effects. Secondly, thereadback and configuration verification method is used to detect SEU fault, based onthe theory of configuration information format, readback command compositionprinciple and configuration data frame addressing modes. Finally, this dissertationemployed dynamic full reconfiguration and dynamic partial reconfiguration to repairthe SEU faults in FPGA’s internal configuration memories.Through the experiments that implemented on the proposed demonstrationplatform, the verification results showed that, with the function of fault positionrecord, the readback and configuration verification fault detection method can detect100%SEU errors within FPGA’s internal configuration memories. The faultcorrection method of dynamic reconfiguration can repair all the SEU errors thathappen in FPGA’s internal configuration memories. Comparing with the dynamicfull reconfiguration, the technology of dynamic partial reconfiguration can reducethe system’s trouble-free operation time and improve failure recovery. With thecombination of above fault detection and correction method, the SEU faults amongSRAM base FPGAs can be tolerant online.