Implement And Reseach On A Pipelined ADC Digital Calibration Algorithm

Pipelined ADC with high speed and high accuracy is widely used in video imaging system, communication system and test equipment. In practical applications, the performance of pipelined ADC is limited by the error of capacitor mismatch, comparator offset, and finite DC gain of the amplifier. With the development of CMOS process, it has become more and more difficult to compensate the error of pipelined ADC through the complex analog circuits; The use of digital calibration circuit can reduce the analog circuit's design difficulty, and be a step to improve the performance of the pipelined ADC new means.Firstly, according to the development of CMOS technology, this article firstly expounds the advantage of using the digital circuit aided design of the pipelined ADC; then introduces the abroad mainstream pipelined ADC calibration algorithm, and analysis their advantages and disadvantages based on the calibration algorithm.Subsequently, this paper analysis all kinds of errors of the pipelined ADC analog circuit structure, and established the corresponding error model, which is the basic of reference ADC adaptive filter and the pipelined ADC calibration algorithm research.Thirdly, it starts with the errors of the pipelined ADC and uses the MDAC transfer function to introduce the basic principle based on the reference ADC and adaptive filter pipelined ADC calibration algorithm. Then the paper put forward the variable step size LMS algorithm to improve the calibration algorithm.Finally, the circuit structure of the calibration system optimized by the pipelining design greatly improves the working frequency of system calibration. And use Xilinx V5-110 T type FPGA simultaneously verifies the calibration results of the variable step size LMS calibration algorithm. The results show that compared with the basic calibration algorithm, variable step calibration algorithm has better calibration performance.