Research And Implementation Of The Digital Calibration Algorithm For Pipelined ADC

In the past decades,“Moore Law”has been confirmed. At the same time, theperformance of digital circuits increases faster than analog mixed signal circuit.The resulting large and growing performance gap is the motivation of this researchtowards a more “digitally assited” conversion interface.The key issue of the digital calibration algorithm of pipelined ADC is how toestimate and extract the error parameter. First, this paper analyzes the main causesof equivalent interstage gain error based on the pipelined ADC architecture,including capacitor mismatch and finite opamp dc gain. Then this paper discussesthe digital background correlation calibration algorithm based on the ADSCmodulation. Because of the problem of the speed of the basic algorithm is low, weuse a split ADC architecture. Finally this paper finishes the gain error calibration ofthe second stage resulting from the MDAC error and the calibration of third-ordernonlinear term in the amplifier.To verify the algorithm of the split ADC, we establish a model of14bitspipeline ADC using c language. The simulation results show that: compared withthe pipeline ADC without using any calibration algorithm, the performance ofpipeline ADC has been improved greatly with the calibration algorithm of splitADC architecture, ENOB enhances from10.58bit to13.94dB, SFDR enhances from82.22dB to107.24dB. The gain error parameter converges in107conversions whenusing the basic correlation calibration algorithm, however the gain error parameterconverges in about7×10~5conversions when adopting the split-ADC architecture, iteffectively accelerates the convergence of gain error.Finally, this paper implements the calibration algorithm on a FPGA board anda DSP board. The above simulation results remain consistent with behavior levelsimulation.