Soft Error Sensitivity Analysis Of SRAM-based FPGA Based On XDL

The task undertaken by the space instrument is more complexable and more precise,which makes the SRAM_based FPGA,with high-performance,low cost,reconfiguration and other advantage,widely used in the space instrument.But it also cause some problem,in which the affluence of single event efficiency(SEE)has taken an important part and will take more in the future with the feature size of integrated circuits reducing.The sensitivity analysis of soft error rate(SER)due to SEE for system in FPGA will offer assistance in discover the soft error vulnerability in design.Therefore,we can predict the system's performance in orbit operation,and make targeted measure to ensure the normal operation.Currently,accelerator test and fault injection has been widly accepted as a sensitivity evaluation of SER for a design.The former is costly and resource lacking.The later is time-consuming and low efficiency.Sensitivity analysis of SER for SRAM-based FPGA based on Xilinx design language(XDL)will be an important method in figure evaluations because of its hign efficiency,high speed and low cost.Research will begin with.ncd file generated in Xilinx FPGA design process,then convert it to XDL netlist and develop SER sensitivity analysis software to acquire circuit information based on Rapidsmith.The research in this paper mainly includes the following works:(1)Judgment method of sensitivity bit.The research on judgment method of sensitivity bit can fix specific configuration bit of each sensitivity bit,which makes a higher accuracy.We also develop the software based on Rapidsmith.Now,the software support SER sensitivity analysis for xc4vsx55 FPGA system.(2)Analysis of XDL netlist to FPGA resource.The paper research the method to describe FPGA resource in XDL netlist,elucidate the grammatical structure of XDL netlist,analysis the relationship between XDL content and FPGA circuit resource in detail and strengthen the congnitive to them,which makes up for obscure description weakness.(3)Analysis of configuration data to FPGA resource.The paper correct the frame address error in xc4vsx55 FPGA published in Xilinx official website,explore the correspondence between programmable interconnect points(PIPs)and configuration bit,analysis the frame structure and configuration data in xc4vsx55 FPGA.The analysis method is suitable for Virtex-5 and higher series FPGA.