Research On Soft Error Evaluation Method Based On SRAM FPGA

Due to continuously progressing technology node,improving integration,increasing frequency,and reduced voltage,nano-dimension IC is becoming more and more susceptible to radiation effects(space radiation,atmospheric radiation,industrial radiation and packaging materials radiation,etc.),resulting in false system output,even leading to system failure.Especially in special aeronautics and astronautics applications,transient failure caused by irradiation effect of high energy particles has seriously affected the reliability of electronic system.For increasingly serious SEE soft error problem,efficient and high-precision soft error assessment has become a hot issue in the field of highly reliable IC design and application.With the increase of the number of nodes in the circuit,the calculation amount for soft error assessment increases exponentially,causing a serious slowdown in the sensitivity assessment,in order to efficiently analyze IC soft error sensitivity to SEU,based on fault injection in SRAM FPGA,we propose a SEU sensitivity analysis method,with the aid of FPGA hardware parallel features,effectively accelerating SEU soft error assessment process.SET has a more complex impact mechanism on soft error sensitivity and is difficult to accurately model,for the sake of accurately analyzing SET soft error sensitivity,FPGA is used as a more real IC emulation platform,in which high-precision generation and detection of real pulse are realized,and the change of pulse width at SET propagation is also studied.In addition,as an extension of the SET propagation research,the paper deeply analyze the effect of both process fluctuation and electronic thermal noise on pulse propagation,and then,a highly reliabile butterfly PUF and a high-efficiency jitter-quantizing TRNG are implemented in FPGAs.The main work is as follows:(1)In order to effectively accelerate SEU soft error assessment process,based on fault injection in SRAM FPGA,the paper proposes a soft error sensitivity analysis method,with the aid of both FPGA hardware parallel features and good modeling ability,emulating abnormal flipping of circuit nodes caused by particle bombardment on the hardware level,the modules such as logic control,fault classification,fault list and other modules are all implemented on hardware for a further improvement of soft error evaluation efficiency.The experimental results show that the proposed SEU soft error assessment method is 3 orders of magnitude higher than the same model evaluation method based on software simulation.(2)To study SET sensitivity for high precision,in this paper,FPGA is used as a more real circuit emulation platform,then SET generation and SET detection are both implemented on chip,the generated SET not only has high accuracy and excellent stability,but also can be adjusted continuously with 100 ps as a step;the SET detector has a detection accuracy of 30 ps,a lower detection limit of 150 ps,a good stability when applied to many kinds of operation environments,and it can detect two-polarity pulses.Based on the proposed SET generation circuit and SET measurement circuit,the SET propagation phenomenon is deeply studied in the paper.The experimental results show that the pulse broadening effect is not related to pulse width,but is directly proportional to the length of propagation chain,and pulse broadening effect is quite different for SET propagation under different polarities.(3)In the SET propagation experiment,having realized the effects of process fluctuation and electronic thermal noise on SET propagation,we deeply study the influence of these two factors on the transition process from metastable state to steady state,and efficiently implementing two important security technologies:a highly reliable butterfly PUF and a high-efficiency jitter-quantizing TRNG In order to improve PUF reliability,we propose a delay difference assessment strategy to identify Slice suitable for PUF mapping,and then we selectively map PUF into the suitable Slice,leading to a great improvement on PUF reliability;In order to improve the randomness extraction process,a purely digital TRNG based on jitter quantization is proposed in SRAM FPGA through TDC circuit with tiny vernier interval,it can digitally snapshot random delay jitter caused by electronical thermal noise.The experimental results show that the proposed TRNG has a low resource overhead of 32 Slice and a high throughput of 127 Mb/s,and it owes good tolerance to bias phenomenon caused by PVTA variations.