Research On Fault Injection And Scrubbing Technique For SRAM-based FPGA

Because of the reconfiguration of field programmable gate array(FPGA),FPGA has been widely concerned and applied.Especially for SRAM-based FPGA,it becomes widely used in commercial and scientific research due to its high performance,large density,fast time-to-market and flexible configurability.Unlike application specific integrated circuit,SRAM-based FPGA can be configured and reconfigured online which makes SRAM-based FPGA is popular in aerospace field.However,due to the architecture of SRAM-based FPGA,its application will be limited in aerospace field.There are a large number of energetic particles in aerospace that can result in single event effects when they strike the integrated circuit,such as single event upset(SEU),single event transient,and so on.SRAM-based FPGA contains a large number of SRAM cells which can generate SEU if they are struck by the energetic particles.For SRAM-based FPGA,SEU is a serious problem because the function of SRAM-based FPGA can be wrong permanently if SRAM-based FPGA generates SEU,unless FPGA is reconfigured.Therefore,it is the international research hotspot that researching the evaluation and fault-tolerant technique to SEU for SRAM-based FPGA in aerospace field.This paper evaluates the reliability to SEU by researching fault injection technique and designs fault-tolerant technique by researching scrubbing technique for SRAM-based FPGA.The main contents of this paper including:(1)Research on fast fault injection technique.Configuration memory is the most important part of SRAM-based FPGA.If SEU occurs in configuration memory,the function of user circuit can be changed directly.Firstly,we make the fault analysis to the SEU in configuration memory of SRAM-based FPGA.Then each procedure of fault injection is researched and optimized respectively to improve the speed of fault injection.We optimize the address generator which can generate effective and even distributed addresses in real time.The even distributed addresses are closed to the real situation in aerospace.This optimized address generator can make the fault injection faster and more accurate.By adopting the pipeline method for fault injection procedures,the flow of multiple SEUs accumulation fault injection is optimized that can improve the speed of fault injection.(2)Implementation of fast fault injection platforms.We implement two fault injection platforms to evaluate the sensitivity to single SEU and the sensitivity to multiple SEUs accumulation.Fault injection platforms can reduce the failure rate by optimizing the placement.Fault injection platforms have self-repair function that fault injection platforms can repair the injected SEUs directly when needed without reconfiguring the whole FPGA.This self-repair function of fault injection platforms not only can improve the system automation but also can speed up the fault injection.The sensitivities to SEU of ISCAS85 circuits are evaluated on two fault injection platforms respectively.Experimental results show that the sensitivity to SEU of user circuit is related to its resource utilization.In general,the higher the resource occupation,the higher the sensitivity to SEU.The sensitivities to SEU of triple modular redundancy(TMR)of user circuits are also evaluated.Experimental results show that TMR technique is good at tolerating the single SEU effect but is not able to tolerate the multiple SEUs accumulation effect.The experimental results also validate the fault injection platforms.(3)Research on the scrubbing technique based on essential bits technology.Scrubbing is an effective technique to improve the reliability to SEU for SRAM-based FPGA.This paper proposes an adjustable and fast error repair scrubbing technique based on essential bits technology.Firstly,this paper researches the Xilinx essential bits technology and identifies the frames related to user circuit in configuration memory.Then the scrubbing flow is devided into two sub-flows,one sub-flow scrubs the frames related to the user circuit and repeats many times in a scrubbing flow,another scrubs the whole configuration memory and repeats once in a scrubbing flow.By scrubbing the frames related to user circuit mainly,the duration time of SEU in user circuit can be decreased.This method can improve the reliability to SEU of user circuit meanwhile can ensure the reliability to SEU of whole FPGA.The experimental results indicate that the proposed scrubbing technique can obviously improve the reliability to SEU of user design for SRAM-based FPGA.(4)Research on the scrubbing technique for TMR-based circuit.TMR is a common and effective fault-tolerant technique for SRAM-based FPGA.However,only adopting TMR is not enough.Usually the combination between TMR and scrubbing can ensure the reliability to SEU of user circuit for SRAM-based FPGA.This paper proposes a fast error repair scrubbing technique for TMR-based circuit.Firstly three redundancy modules of TMR circuit are placed respectively.Th en the majority voter of TMR circuit is optimized.The optimized majority voter can identify the wrong module from three redundancy modules.Scrubber will scrub the wrong module firstly.The proposed scrubbing technique scrubs the module based on frame which is more flexible than the scrubbing techniques based on module.This scrubbing technique does not need additional storage to store the original frame data.The experimental results indicate that the proposed scrubbing technique can obviously improve the reliability to SEU of TMR-based circuit for SRAM-based FPGA.This paper studies the SEU in SRAM-based FPGA,and proposes fault injection and scrubbing techniques for SRAM-based FPGA.This techniques all have practical significance in aerospace application.