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Design And Implementation Of Single Event Test System (SETS) For Static Random Access Memory (SRAM)

Posted on:2016-12-19Degree:MasterType:Thesis
Country:ChinaCandidate:J T GaoFull Text:PDF
GTID:2272330482951571Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
The research on Single Event Effect (SEE) mechanism of Integrated Circuits (ICs) has become one of the most attractive topics in the field of Radiation Hardening (RH). Static Random Access Memory (SRAM) is a kind of essential circuit in aerospace. But it is also very sensitive to Single Event Upset (SEU) effect. In order to research on the SEE mechanism at chip level and precisely evaluate SRAM’s capability for resisting the high energy particles, it is extremely necessary to design and implement a reliable and common-use SRAM Single Effect Test System (SETS).This SRAM SETS is designed to evaluate general SRAM’s capability to resist SEE. The capacity of target SRAMs can be 64K~1M or bigger. According to the requirements of testing purpose, target circuit’s function and testing environment, this SETS includes lower-computer, power supply and host-computer. One feature of the test system is that it’s the first time in our lab to design such a test system by taking both advantages of Field Programmable Gate Array (FPGA) and Virtual Instrument (Ⅵ). FPGAs have rich programmable resources, especially digital IOs. And it is very easy to implement a System on Chip (SOC) on FPGA to implement a lower-computer. The lower-computer has many advantages, such as easily programmable, little volume, light weight, portable and relatively low cost. It can also significantly shorten the distance between test system and the target circuit, and eventually enhance the whole system’s reliability. By using the virtual instrument software Lab VIEW to control the Keithley 2400 and FPGA based lower-computer, a high degree of accuracy of both the controlling voltage and collecting current can be achieved. The control interface of host computer is friendly and very convenient for the following updates.The SETS are built on multiple advantages in different aspects, such as the small-size and reliability of FPGA, the excellent drive ability of power supply and high testing accuracy of source meter, the powerful equipment control capability and simple following upgrade of Lab VIEW software. The design of this system has been completed. It has been used many times in Beijing HI-13 tandem accelerator. The test results showed that this system is stable and reliable. Abundant and reliable experimental data has been provided for the scientific research. This test system can be applied in all domestic accelerators testing environment.
Keywords/Search Tags:SEU, SEL, FPGA, SRAM, LabVIEW
PDF Full Text Request
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