Research On Key Technologies Of SRAM-based FPGA Single Event Effect Fault Injection Test Method

For its high-performance, reconfigurable and other advantages, SRAM-based FPGAs are more and more widely applied in space instrument design. However, due to its sensitivity to Single Event Effects(SEE) in space environment, mitigation techniques are necessary before application. The performance of different mitigation techniques requires accurate verification in order to give a reference to designers. Currently, test based on high energy ions accelerator is the “golden standard”. But in our country, the accelerators are quite lacking. And the construction of accelerator is costly and time-consuming. Coupled with there are some unavoidable disadvantages in accelerators test. Research on the alternative test method is imperative. SEE fault injection as a new test method, with its advantage of high efficiency, flexibility, low cost, etc., in the foreseeable future, will become an important role in the single event effects test.This leads to the fundamental question of this article: How to use fault injection to test the performance of SRAM-based FPGA mitigation techniques. To solve this problem, the thesis focuses three key technical issues faced by SRAM-based FPGA SEE fault injection testing methods:(1) Fault injection model problem.SRAM-based FPGA fault injection model is the essential proem of fault-injection test, whose accuracy determines the validity of the test results, and it is also necessary to take into account the existing technical conditions of fault injection. It is the first key technical issue to establish an accurate fault injection model which is the input of a fault injector.(2) Fault injection testing and evaluation methodologies.Fault injection is essentially different from the traditional accelerators test in mechanism. What is the correspondence between test results obtained by fault injection and by accelerators test? How to evaluate the performance SEE mitigation techniques for SRAM-based FPGA through fault injection is the second key technical issue.(3) Testing time explosion problem.In conditions of traverse the spatial and temporal fault set, fault injection experiment requires a lot of time overhead. How to improve test efficiency with lest effect to the accuracy of the result is the third key technical issue.To solve the above key technical issues, this thesis presents a fault injection model, proposed a test method to evaluate the performance SEE mitigation techniques for SRAM-based FPGA through fault injection, which proposes an approach for improving the efficiency of fault injection test, designs and implements a SRAM-based FPGA SEE fault injection testing system, carries out some test using this system, and verifies this result with HI-13 tandem accelerator. The results proved the feasibility of fault injection test method. The work of this thesis provides a theoretical and practical support for further application of SRAM-based FPGA fault injection.