A Reconfiguration Design And Implementation Of H.264/AVC CAVLC Entropy Coding With FPGA

With the rapid development of digital video technique, video compression become more and more broadly, however people demand higher and higher in video compression. In recent years, The International community launchs mpeg-4and H.264/AVC video compression standards, they play a great role for the future of digital television, wireless video and the development of the industry.H.264/AVC standard is the most mainstream video compression standard, it has many advantages for example wide range, meeting different rate. Compared with the previous code, the coding efficiency can be improved. H.264includes two kinds of entropy coding: Context-adaptive variable-length coding (CAVLC), Context-adaptive binary arithmetic coding (CABAC). This paper mainly studies the CAVLC, it can choose the best code table according to the previous code data, and find out the best matching code table to code with the current coding data statistical properties.Dynamic Partial Reconfiguration is the best mainstream reconfigurable technology and also is the research focus in currently. It can achieve the hardware circuit which has many advantages for example high speed and high resource utilization through the dynamic partial reconfiguration technology. The topic of this article is to research context-adaptive variable-length coding (CAVLC) of h.264/AVC video coding standard and design and implement the reconfiguration modules. This paper studies as follows:(1) This paper briefly introduces the concept of video compression and the development history and key technology of h.264coding standard. This paper deeply analysis the encoding and decoding process of h.264, especially the elements of CAVLC encoding/decoding process and the implementation process.(2) This paper simply reviews the concept and programming technology of FPGA, and deeply analysis the internal structure and design process of FPGA. After analysis the reconfiguration concept and principle of FPGA, the paper classifies the reconfiguration technology according to the different methods of reconfiguration, points out the advantages and disadvantages of them through comparing with each other and finally this paper chooses EAPR design method.(3) This paper briefly introduces the Verilog HDL hardware description language, writes the CAVLC encoding/decoding reconfiguration modules with Verilog HDL hardware language and has comprehensive verification. Because the traditional look-up table is more tedious and the needs of logic resources is more, therefore, this design uses the method of based on "son-table" to search. Another method is to use checking the first "1" method(making each column of the table as a state, then continue to divide according to different methods), which speeds up the search speed and economize resources.(4) After grasping the EAPR process and technology, author makes VirtexⅡ Pro XC2VP30device for development platform of Xilinx company and put forward a design method which make CAVLC encode/decode of h.264true through dynamic partial reconfiguration method, and finally verified by practical example. Through analysis experimental data, this paper points out the advantages of dynamic partial reconfiguration method.