Low-power Digital Transmitter With Envelope Pulse-width And Phase Differential Modulations

In recent years, with the application of all kinds of portable wireless communication products, the rise of implantable medical devices, and the rapid development of wireless body area network and wireless personal area network, people have high requirements for low power consumption, high efficiency, and low complexity of transmitters. Besides, the trend of high spectrum efficiency and high data rate causes a variety of non-constant envelope modulation methods working in different frequency bands. In order to ensure good channel inhibition and low signal distortion, high linearity and multi-mode multi-band features are required.Polar modulation is a good choice among many transmitter configurations to archive such goals. With feasible innovations of digitized envelope modulation, full-differential phase modulation, and simplified path delay alignment, this project aims at a feasible system solution to low-power, low-complexity, high-efficiency, high-linearity, and multi-mode multi-band transmitters, based on existing polar architectures and the developing trend. Phase path employs a differential Delta-Sigma modulated dual-path voltage-controlled oscillator, to implement the conversion from baseband-frequency digital phase to radio-frequency constant-envelope one. The voltage-controlled oscillator employs distributed biasing and full-differential technique to improve the modulation linearity. An automatic frequency correction loop stabilizes the carrier frequency. Envelope path uses a digital pulse-width modulator to drive a power inverter followed by an LC filter, implementing the conversion from digital envelope to analog one and enabling large-current driver capability at the power supply of the following switched-mode power amplifier. To ensure the precision of delay modules, a unit delay automatic correction loop is employed.This paper firstly introduces the research background of transmitters, compares and analyzes several kinds of traditional quadrature and polar transmitter architectures. Then, the polar transmitter configuration is proposed and the critical submodules of modulation paths are clarified. The schematic design and system simulation are implemented in UMC 180 nm CMOS with a 1.8V supply, and the layouts of some critical modules are completed. The simulation results show that the transmitter phase noise is-124.9dBc/Hz at 400 kHz offset frequency, and the system error vector magnitude is 4%, which meet 8PSK(EDGE) communication system requirements.