Aging Characteristic Analysis And Aging-mitigation Design For Power-Gating Circuit

In modern integrated circuit design, using power-gating technology to reduce static power consumption has become a mainstream trend. With the scaling down of feature size of integrated circuits, the reliability of integrated circuit is getting increasingly important; Bias temperature instability (BTI) which causes circuit aging has become an important factor when it comes to reliability of integrated circuits. When the power-gating circuit is in normal operating mode, sleep transistor is affected by BTI severely, which lead to the increasing performance loss of power-gating circuit.In the existing aging characteristic analysis of power-gating circuit, the relationship between performance loss and aging effect hasn’t been taken into consideration, thus the model of performance loss considering aging effect is still lacking. In this thesis, we consider the impact of BTI caused aging of sleep transistor and logical network on power-gating circuit, and establish a performance loss model caused by BTI aging effect. Through analyzing two different types power-gating circuit (header-based and footer-based), it is demonstrated that the aging performance loss models for the two types of circuit are consistent. The results show that the trend of calculated value based on the aging performance loss model is consistent with the trend of actual value simulated by HSPICE.In header-based circuit aging mitigation, the traditional design is always too pessimistic to set all the sleep transistors in on-state, which would aggravate the sleep transistor aging and lead to header-based circuit performance loss. Through analyzing the header-based circuit aging characteristics, we propose to group the sleep transistors. In this way each transistor group turns on periodically to dynamically adjust the sleep transistor size or their on-resistance, so that part of the sleep transistors are always in recovery state, thus reducing the header-based circuit performance loss caused by sleep transistor aging. HSPICE simulation results under 45nm node technologies show that compared with the traditional method, the proposed method can boost the lifetime of header-based circuit about 30%.In the existing footer-based circuit aging mitigation, the stress-probability control method not only lack of sleep transistor grouping mechanism research but also did not consider the minimal sleep transistor size in designing. For these reasons, a new sleep transistor grouping method based on minimal size is proposed; combining with the dynamic sleep transistor over-sizing and stress-probability control method, we set different groups of sleep transistor breakover in turn periodically. When the performance loss reaches the threshold we set in advance, dynamic sleep transistors over-sizing method is applied. By gradually increasing the sleep transistor size, the switching strategy is optimized. HSPICE simulation results under 32nm node high-k technologies show that compared with traditional sleep transistor switching strategy, the lifetime of footer-based circuit can be increased by 8.8% by using the proposed sleep transistor switching strategy.