Investigation Of Device Degradation In P-channel Ply-Si Thin Film Transistor Under Dynamic Negative Bias Temperature Stress

Degradation of p-channel poly-Si thin film transistors (TFTs) under dynamic negative bias temperature (NBT) stress has been studied. A two-stage degradation behavior is observed for the first time under the dynamic NBT stress. Device threshold voltage (Vth) shift towards positive values in the first stage to more negative values in the second stage. The Vth positive shift is thought to due to the dynamic effect under dynamic NBT stress and which will saturate after a long time stress. The dynamic effect is more significant under dynamic NBT stress with shorter pulse falling time and/or higher pulse amplitude. The negative charge generation in the gate oxide during the dynamic NBT stress is thought to be responsible for the positive Vth shift, while the well-known DC NBTI effect causes the negative Vth shift. A degradation mechanism is proposed to explain the negative charge generation under the dynamic NBT stress. The degradation model has been verified by both simulation and experimental resultsThe stress induced hump appearance and vanishing in the sub-threshold region is observed. The hump appears in the first stage of the degradation under dynamic NBT stress. The presence of parasitic edge transistor at the channel width side is thought to be responsible for the hump phenomenon. Based on our proposed degradation model under dynamic NBT stress, the device composed by a main transistor and two narrow edge transistors is introduced to clarify the hump phenomenon by considering the different Vth shift of the main transistor and two parasitic edge transistors. The well fitting result further proves the proposed degradation mechanism.