Research On Low Cost High Reliability Power Gated SRAM Design

With the progressing of the technology, the size of the transistor is becoming smaller and smaller, and the microprocessor design has evolved from the micrometer era, represented by Intel 4004 which is designed in 10 um at 1971, into the nanometer era, represented by Intel CoreTM i7 4770 k which is designed in 22 nm at 2013. These improvements bring up not only the higher and higher performance, but also the side effects. The power is ever increasing, and the reliability problem is becoming more and more serious. In nanometer era, the low power design and the reliability-aware design have become among the first-class considerations.SRAM is the most popular unit in the modern microprocessors and SoCs. It takes the largest area and largest amount transistors. The magnitude makes SRAM be the main source of the leakage power. Power gating design is applied to reduce the leakage power. To improve the magnitude of the integration, SRAM takes the smallest design rules, which makes it be prone to be affected by aging effects. Among them, the Bias Temperature Instability(BTI) effect was regarded as one of the most serious reliability problems in SRAM design.The thesis focuses on the low cost high reliability power gated SRAM design. It works on three aspects, the low cost reactivation scheme, and the impacts of BTI effects on power gated SRAM and the low bounce BTI-recovery enhancing circuit design in power gated SRAM. The main contributions are as follows:1) A high power-efficiency reactivation scheme is proposed. The transition power and transition delay during the state transition are the main sources of the cost in the power gating design. To get a high power efficient reactivation, this thesis proposes a charge-recylcing circuit. It can reduce the transition energy and delay, and get a lower the rush current at the same time, which could increase the circuit reliability. The experiments results shows that, it can achieve 18.40% reactivation energy reduction, 3.27% peak leakage reduction, and 9.73% wakeup delay reduction, at 25℃, at the cost of 1.11% area increasing. At the same time, the ground bounce is reduced significantly since the large reduction in rush current.2) A signal probability and activity probability model(SPAP) is proposed, to estimate the BTI effects on power gated SRAM. The experiments results shows that PBTI has significant influence on the read and write operation of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. The statistic data of CPU2000 benchmarks shows that the proposed model has an average of 3.85% SNM relaxation for 106 s working time compared with previous work.3) A low bounce BTI recovery enhancing circuit based on the BTI recovery mechanism is proposed. By making use of the recovery mechanism of the BTI, it can make the power gated SRAM enter into the BTI recovery mode in one cycle time, and back to normal working state in a few cycles, to reduce the side effects of the BTI effects. A bypass power line and a bypass ground line are introduced to reduce the main power/ground line bounce, from over 100 mV to less than 10 mV, which improves the reliability of the whole SRAM arrays.In a word, our proposed fast reactivation circuit can reduce its mode transition cost by charge sharing, and the SPAP model can provide a quantificational analysis of the impacts of BTI effects on power gated SRAM, and the proposed low bounce BTI recovery circuits helps to get a quickly transistion between the working mode(BTI affected) and the BTI recovery enhancing mode. So the researches in this thesis show us a high power efficient high reliability power gated SRAM design, and could give a strong support for the broader application of the power gated SRAM.