Degradation Mechanisms Of Poly-Si Thin Film Transistors Under Static And Dynamic Voltage Stress

Degradation behaviors and mechanisms of low temperature poly-Si (LTPS) thin-film transistors (TFTs) under static and dynamic voltage stress are systematically investigated in this work. We focus on TFT degradation under DC positive bias temperature (PBT) stress, degradation under dynamic PBT stress and TFT degradation under drain pulse stress with gate and source grounded.1. TFT degradation under DC PBT stressTwo-stage degradation behavior is first discovered in p-channel poly-Si TFTs under DC PBT stress. In the first-stage degradation, after initial1s stress, on-state current (Ion) increases about3%associated with a positive threshold voltage(Vth) shift (-0.12V). Then a gradual Ion decrease is followed, although ΔIon is still positive. However, as stress continues to～1000s, Vth begins to shift to the negative and Ion degrades markedly with stress time, leading to the second-stage degradation. A comprehensive two-stage degradation model is proposed based on the above experimental results. The first-stage degradation is dominated by electron trapping in the gate oxide near the interface via Fowler-Nordheim (F-N) tunneling, leading to the observed initial Ion increase and positive V,h shift. However, trapped electrons could be re-emitted through Poole-Frenkel (P-F) emission, resulting in the slight Ion decrease. In the second stage, similar reaction in the NBTI is responsible for the degradation. Positive charge generation in the gate oxide is the dominant mechanism for the significant Ion degradation and negative Vth shift.2. TFT degradation under dynamic PBT stressDifferent from the monotonic increase of Ion in previous work, Ion exhibits two-stage degradation behavior. However, this two-stage degradation behavior is different from that of DC PBT stress. Some new degradation mechanisms are involved. In the first-stage degradation, Ion continuously increases with stress time with a slight positive Vth shift. After a long-term stress, Ion degrades abruptly, leading to the second-stage degradation. However, it is worth emphasizing that severe carrier mobility degradation dominates the two-stage degradation while Vth varies slightly. To better understand the degradation under dynamic PBT stress, it is essential to study the degradation mechanisms during different parts of the pulse stress. Based on the experimental and simulated results, a new two-stage degradation model is proposed. The first-stage degradation is attributed to channel length shortening effect induced by electron trapping, which is responsible for the gm and Ion increase. Whereas in the second stage, dynamic HC effect related trap state generation is the dominant degradation mechanism, causing the significant Ion decrease due to the server carrier mobility degradation.3. TFT degradation under dynamic drain pulse stressIn our previous work, it is found that n-type poly-Si TFT suffer serve HC degradation under drain pulse stress with source and gate grounded, which is similar to dynamic HC degradation under gate pulse stress. In this work, p-channel poly-Si TFTs under dynamic negative pulse stress is investigated. Similar degradation occurs in p-channel TFTs, which strongly depends on pulse falling time but is independent of pulse rising time. The experimental results can be well explained based on our previously proposed non-equilibrium PN junction degradation model. However, in the initial stage, dynamic HC degradation can not occur immediately, and degradation is dominated by the equivalent DC effect. Electron injection due to DC effect will cause lots of deep trap states in the interface. With the presence of deep traps, the non-equilibrium PN junction degradation can be triggered.