Degradation And Recovery Mechanisims Of Low Temperature Poly-Si Thin Film Transistors Under Static Voltage Stress

In this paper,degradation behaviors and mechanisms of solution-based excimer laser annealing(ELA)n-type low temperature polycrystalline silicon thin film transistor(LTPS TFT)are systematically investigated under direct current(DC)gate and drain bias stresses.Recovery behaviors and mechanisms of TFT after removing the stresses are also studied.The DC bias stresses applied to the devices mainly include:positive gate stress and positive drain stress,negative gate stress and positive drain stress,single positive or negative gate stress,and single high positive gate stress.1.TFT degradation and recovery under positive gate bias stressesIt is discovered that the devices under positive gate stress and positive drain stress experience significant hot carrier(HC)degradation.After removing the stress,the time dependent recovery feature is first discovered.The on-state current(I_on)of the device decreases non-linearly.After 6000s stress,the I_on decreases more than 95%.In the recovery stage,the I_on increases reversely,and 4000s after removing the stress,the I_on recovers 7%.We propose that the DC HC effect causes a self-recovery degradation feature based on the above experimental results.In order to exclude the effects caused by other mechansims under the stress,the single positive temperature bias instability(PBTI)condition is considered.It is found that the degradation is greatly weakened and the recovery does not occur under the positive bias stress.We can conclude that the degradation mechansims of the DC HC stress and the PBTI stress are different,and different recovery features are generated,after removing the stresses.Only the DC HC effect produces a degradation feature that is self-healing.2.TFT degradation and recovery under negative gate bias stressesIt is discovered that the devices under negative gate stress and positive drain stress also experience HC degradation even if the devices are in the off-state.After removing the stress,the time dependent recovery feature is also discovered.The degradation and recovery trends of I_on are the same as those under DC HC effect.Based on the recovery experimental results,we propose that the core influence factor of DC HC degradation mechanism is the lateral electrical field along the channel provided by the drain stress,rather than the vertical electrical provided by the gate stress or the carrier concentration formed in the channel.The devices with only NBTI stress show weak degradation and no recovery feature,which excludes the role of the gate-forming vertical electric field on the self-healing degradation.As long as the lateral electric field is present,the DC HC degeneration occurs regardless of whether the device is on or off.3.TFT degradation and recovery under single high positive gate stressDifferent from the results in previous works,two-stage degradation feature is observed in n-type LTPS TFT under high PBTI stress.In the first stage,the devices are within 100s of applying PBTI stress.As stress time increases,the threshold voltage(V_th)is shifted to the positive direction,and I_on decreases gradually.When the stress continues to 6000s,the V_th begins to be shifted to the negative direction and the I_on increases with stress time,leading to the second-stage degradation.We determine that the combination of at least two degradation mechanisms leads to the occurrence of the two-stage degradation feature.The poly-Si/SiO₂ interface traps are generated under high PBTI stress.The energy band bends and the intermediate level is gradually below the Fermi level.The acceptor traps are occupied by the electrons,which induces the first-stage degradation,resulting positive V_thshift and decrease of I_on.In the second stage,hole defects are generated in the insulating layer and gradually dominate the degradation,causing negative V_th shift and increase of I_on.