DC Gate Bias Stress Induced Degradation Of ELA Poly-Si TFT And EMMO A-IGZO TFT

In this work,we focus on the device reliability of P-type ELA(Excimer Laser Annealing)poly-Si thin film transistors(TFTs)and EMMO(Elevated-Metal Metal-Oxide)amorphous In Ga Zn O(a-IGZO)TFT under DC gate bias temperature stress.The degradation behaviors and mechanisms are systematically investigated and analyzed,and some degradation models are proposed.1.P-type ELA poly-Si TFTFirstly,the optimized process crystallization condition(470 m J/cm2 to 510 m J/cm2)is obtained by investigating the properties of poly-Si films and the performance of poly-Si TFTs fabricated on the poly-Si films with different laser energy densities.It is observed that the transfer characteristics continuously shift towards the negative gate-voltage direction under negative bias temperature(NBT)stress.The degradation mechanism of NBT instability is attributed to hydrogens derived from the broken Si-H bonds,which react with Si Ox and positive charges(Si+)are generated in the gate oxide.Nevertheless,a two-stage degradation,which is relatively complicated,is observed under positive bias temperature(PBT)stress.In the first stage,threshold voltage(Vth)shifts in the positive gate-voltage direction accompanied with on-state current(Ion)increasing,and a hump is observed in the subthreshold region of the transfer characteristic.While in the second stage,Vth shifts negatively and Ion decreases,and the degree of degradation is much more significant than that in the first stage.It is proposed that the first-stage degradation is mainly due to electron trapping into gate insulator via Fower-Nordheim tunnelling,whereas the second-stage degradation is dominated by the accumulation of hydrogen ion(H+)at the interface and the generation of Si+ in the gate oxide.2.EMMO a-IGZO TFTUnder the action of PBT stress,an abnormal degradation behavior is observed in EMMO a-IGZO TFTs.A hump-effect appears in the subthreshold region after applied a certain time of PBT stress.And as stress time increases,both the on-state current and the hump shift towards the negative gate-voltage direction.Therefore,we propose that the positive charges trapped at the back-channel interface causes the negative shift.The humps arise at almost the same current levels for devices with different channel widths,which indicates that the hump effect is due to more positive charges trapped at the edges along the channel width direction during the period of PBT stress.On the other hand,the hump effect becomes more significant in short channel devices.It is proposed that the diffusion of oxygen vacancies take place from the high concentration source/drain region to the intrinsic channel region.