Design Of A 12 Bits 30MS/s SAR ADC Based On 0.35μm CMOS Process

As an embranchment of Nyquist ADCs, successive approximation register (SAR)ADCS have been widely used in wireless sensor networks, cable communication, cellular phone, hard disk drive, data storage and digital video due to its high power efficiency, low cost and simple structure.Based on the requirements of high speed wireless sensor networks, a 12bit,30MS/s low-power successive approximation ADC is designed in this thesis. This paper researches and designs the unit circuits which can increase the conversion rate, improve the accuracy and reduce the power consumption of SAR ADC. In order to increase the sampling accuracy of SAR ADC, an improved bootstrapped switch is used to realize the sampling and hold circuit. Segmented capacitor arrays are used to realize the DAC circuit, which method can reduce DAC area and increase the power efficiency. To ensure the piecewise of DAC, the high array uses a thermometer encoding. And to improve the matching accuracy of the capacitor, DAC layout adopts the way of common mass center. The preamplifier with large latch comparator is used to reduce kickback noise. And the added regulating resistance improves the delay time. In order to reduce the circuit area and the dynamic power consumption, the SAR control logic uses the dynamic latch to store the comparison results. The layout of SAR ADC and system simulation results are showed in this paper. Finally, this paper discusses the test results of SAR ADC. The design of SAR ADC is implemented in 3.3V TSMC 0.35μm CMOS process. The area of layout is 0.98mm2. The simulation results show that:when sampling speed is 30MS/s, signal to noise and distortion ratio is 69.0dB, spurious free dynamic range is 76.1dB, the effective number of bits is 11.2bit and power consumption is 13.4mW. Simulation results show that this design meets the system design specifications.