Research And Design Of DDR4 Controller Based On AXI Bus

DRAM has undergone several technological innovations as the increasingly requirement of memory performance.DDR4 SDRAM is the mainstream memory in the current market.At present,the working frequency of memory is far behind that of the processor,which has affected the performance of the overall computer system.As a bridge between the system and the memory,the memory controller is one of the key factors determining the overall performance of the computer system.The commercial IPs of memory controller currently on the market mainly come from foreign companies,and there is still a big gap in domestic technical strength compared with foreign ones.In recent years,the research in this field by major domestic universities has basically stayed at the stage of DDR2 SDRAM and DDR3 SDRAM,and there are relatively few studies on DDR4 SDRAM and DDR4 controller.Based on the enterprise cooperation project,this thesis studies DDR4 SDRAM.On the basis of in-depth understanding of its internal structure and basic timing characteristics,a design scheme of DDR4 controller based on AXI4 protocol is developed,which can convert system bus transactions into DDR4 protocol compliant memory commands of the DDR PHY interface.The thesis introduces the overall design scheme of the memory controller and the design scheme of three main functional modules in the memory controller: AXI interface module,DDRC module and protocol conversion module.First of all,this thesis proposes a new address mapping method in the DDRC module,which combines cross-address mapping and XOR logic,so that the open rows are scattered to different banks of different bank groups to reduce row conflicts,and at the same time,it also prevents individual banks from being fully loaded and other banks being idle.Secondly,according to the characteristics of DDR4 SDRAM with shorter command delay between different bank groups,a new instruction reordering method is proposed,which can combine the traditional open page strategy with the instruction interleaving between bank groups,and classify the read and write instructions to reduce the switching between read and write,so as to improve the read-write efficiency of the memory controller.Then,the read and write commands are converted into DDR4 SDRAM memory commands in the protocol conversion module to be issued in accordance with the timing of Xilinx DDR PHY.Finally,a verification platform is built to perform functional verification and FPGA prototype verification of the designed memory controller respectively.The verification results show that the design in this thesis meets the expected index requirements.The address mapping mode and instruction reordering mode of DDR4 controller are optimized in this thesis.The DDR4 controller designed in this thesis has high read-write efficiency and supports the latest AXI4 bus protocol in the industry.When verifying the memory controller in this thesis,the physical layer chooses to integrate the Xilinx DDR PHY to facilitate FPGA Prototype Verification.After verification,the function of the memory controller designed in this thesis is correct.And it can successfully access DDR4-1600 memory particles at a frequency of 200 MHz,and provides a bandwidth of up to 6.17 GB/s.The read-write efficiency can reach 51.76%,which meets the requirements of this design.After comparing the memory controller designed in this thesis with Xilinx IP,it is found that the utilization of resources and power consumption are close to those of Xilinx IP.