Research And Design Of High LDPC Decode Algorithm In The Transmission Of High Definition Of TV

With the rapid development of mobile communication, generation after generation commercial systems have been developed, and research and development is now under discussion in the fifth generation mobile communication systems(5G) is growing at an alarming rate came to people’s lives, which in the 5G various scenarios inside, the user experience on a very important position. In time to provide users with high-definition video(HDTV) services, to meet the rate and other indicators 5G, the buffer length of time high-definition video is a direct result of the user experience is good or bad feelings. At present, for the concept of high-definition video transmission services in mobile communication applications, technologies, methods are mature, and the degree of attention to user experience feelings is not very high, so to meet the high-throughput 5G channel decoder design aspect, to minimize delays and improve the user experience feel is necessary.Firstly, high-definition video(1920 * 1080, 25fps) transmission and some of the standard gives a brief introduction, analysis of high-definition video application scenarios require coding rate, the buffer length of time factors, the channel decoder buffer delay the length of time of impact, and LDPC because of its superior performance and efficient iterative decoding algorithm attention, at the minimum level and LDPC decoding algorithm traditional hierarchical amendment made some improvements to enhance throughput for HD video transmission throughput requirements, reduce the initial buffering time high-definition video. Chip implementation is Xilinx’s Vertex-7 VC709. On RTL-level design synthesis, placement and routing steps. Considering the five core decoder in modelsim simulation platform, the platform contains a chip Vertex-7 on Xilinx’s board-level testing conducted. Finally, the entire decoder throughput reached 6.3Gbps, the clock is 250 M, quantified as 6bit, a fixed number of iterative decoding is eight times. Resource consumption by 46%.The advantage of high speed, the disadvantage is the chip consumes more resources.