Research On LDPC Encoding And Decoding Technologies And FPGA Design

LDPC (Low Density Parity Check) codes is a kind of linear block codes that defined by very sparse parity matrix or tanner graph.LDPC codes is a kind of the near Shannon Limit error-correcting codes, and its decodmg complexity and error floor are low. For long code lengths, LDPC codes can even outperform Turbo codes,so it is far more likely to be accepted as the Error-Correcting scheme of the fourth generation mobile communications standard. LDPC codes is a research hotspot in the coding field currently.The encoding/decoding theory and FPGA implementation of LDPC codes are deeply studied in the thesis. The main research work is as follows:(1) With regard to the theory research, several construction methods of parity-check matrix,including Gallager codes,Mackay codes,PEG codes and EG codes are analyzed in this thesis firstly.Then the performance of the efficient encoding algorithm using special sparse parity check matrix is explored by comparing it with the conventional encoding algorithm.Finally,the decoding algorithm is deeply studied, emphasizing on analyzing the performance of LDPCcodes at different conditions.(2) An effective decoding quantization scheme for the accepted QC-LDPC code word is obtained based on the Min-Sum decoding algorithm. it remains good performance near to the floating decoding. Finally, the FPGA design of the encoder based on the Two-Stage Encoding algorithm and the decoder based on the Min-Sum decoding algorithm is completed with VHDL language on ISE10.1 platform.(3) The decoder architecture is improved to increase of efficiency and reduce the cost of hardware resources in this thesis. First, the decoding efficiency is improved two times than the old decoder by decoding two frames simultaneously ,but the cost is the slightly more hardware resources.Second,the number of nodes executed in parallel can be selected more freely by storing a set of nodal data in a separate address space;Third, the extrinsic message memory space can be reduced by half by multiplexing variable-to-check message and check-to-variable message into the same memory space.