Research And Implementation Of Parallel LDPC Encoding And Decoding Algorithm Based On FPGA

The successful commercialization of 5G millimeter wave technology has proved that the shortcomings of 5G such as poor penetration and narrow frequency band can be solved by millimeter wave in high frequency band.E-band millimeter wave has the advantages of large bandwidth,strong penetration and low delay,which provides a solution for the future communication system to achieve high-speed communication.In this thesis,the parallel LDPC encoding and decoding algorithm and hardware implementation method for E-band millimeter wave high-speed communication system are studied.In this thesis,three special check matrices are constructed by PEG algorithm and quasi-cyclic structure,aiming at the problem that the structure of random check matrices is too random: QC＿PEG check matrix based on double diagonal structure,the quasi-cyclic check matrix is constructed based on PEG algorithm,and the check matrix is constructed based on PEG algorithm.Then,the performance curves of the three matrices under the optimal decoding parameters are compared by simulation on the MATLAB platform,and the quasi-cyclic check matrix with double diagonal structure is selected as the research matrix of this thesis,and the appropriate quantization scheme is determined.Secondly,in order to solve the problem of high complexity of coding,according to the double-diagonal structure and quasi-cyclic characteristics of the check matrix,a low-complexity recursive coding algorithm is proposed.The XOR operation is performed on the information sequence to obtain temporary data,and the recursive operation is performed on the temporary data to obtain the check sequence.The coding result is obtained by splicing the information sequence and the check sequence.Finally,in view of the high speed requirements of the millimeter wave communication system,this thesis designs and implements a fully parallel decoding structure,allocates processing units for each check node and variable node,and skillfully uses multi-level comparators to resolve the difficult minimum operation in the update process of check nodes.The FPGA hardware implementation of the encoder and decoder in this thesis has been completed based on the Vivado platform.Hardware testing of the encoder and decoder based on FPGA board shows that at a clock frequency of 200 MHz,the encoding throughput can reach 13.3Gbps and the decoding throughput can reach 4.71 Gbps.