The Design Of Memory Test Module Based On USB Bus

As an important part of the computer system, memory modules(memory bank) are the ultimate expression form on the PC. With the improvement of the memory performance and the increasement of integration level, the test of memory is becoming more and more important. To meet the need of memory test, a memory test module based on the USB is designed in this thesis, which is used to test the malfunction of DDR2 SDRAM and DDR3 SDRAM.According to the test requirements, the fault models of the memory are analyzed and several common fault test algorithms are introduced in this thesis. For the case that fault coverage and algorithm complexity of these algorithms cannot easily be balanced,two more superior algorithms are proposed to test the fault of memory in this thesis.Displacement algorithm is used to test external data bus and the settled fault and the bridging fault of the external data bus can be detected. To test the internal storage units,a new March chessboard algorithm based on the March C algorithm and the chessboard algorithm is proposed in this thesis. This algorithm can detect the stuck-at fault, address decoder fault, state coupling fault, transition fault, bridging fault, idempotent coupling fault, inversion coupling fault and dynamic coupling fault of storage units.On the basis of the study on the algorithm of memory fault test, the hardware design and the logic design are accomplished in this thesis based on the USB bus memory test module. Hardware design consists of the FPGA programmable logic device with its configuration circuit, the bus interface circuit of DDR2, DDR3 SDRAM and the USB bus transferring circuit. FPGA programmable logic device is the carrier of logic design, which is primarily used to control the read and write operation of memory bank and deal with the data of the memory fault test. The bus interface circuit of DDR2 SDRAM and DDR3 SDRAM is mainly used to transfer the data and orders of the memory. USB bus transferring circuit is the communication bridge of the memory test module, and mainly used to complete the communication between the computer and the memory test module.The part of logic design consists of SPD data read logic module, memory controller logic module, memory fault test logic module and USB interface transfer logic module. SPD data read logic module is used to read the SPD data of the memorybank, and get the information of memory bank such as type, voltage, capacity, various operation timing and so on. These data are also used to initialize the configuration of the memory bank. Memory controller logic module is mainly to initialize the memory of DDR2 and DDR3 SDRAM, and to read、write and refresh the data, and so on. Memory fault test logic module is used to test and locate the fault of the memory according to the test algorithm, and transfers the result to the host computer by the USB interface transfer logic module.After the debugging and verification of the entire module, the memory test module of this design can test and locate the fault of DDR2 and DDR3 SDRAM, which satisfies the design requirement and achieves the desired goals.