Research On Modeling Of Multi-channel DDR SDRAM Controller Based On SystemC

SystemC-based next-generation DSP modeling and design is designed to meet the real-time processing needs of next-generation multi-channel,high-bandwidth signal processing systems,combined with the status quo and development trends of international mainstream DSPs,to improve the processor's actual computing,storage,and transmission capabilities.The purpose is to provide support for the development of Huarui 3 processor chip.This article takes this project as the research background and completes the modeling task of multi-channel DDR controller based on SystemC.The main work and innovations are as follows:Firstly,based on the DSP modeling project,we designed and implemented a multi-channel DDR controller model based on SystemC.This article uses transaction-level modeling methods to divide the model into multiple sub-modules,such as storage arrays,channel controllers,command queues,and memory request dispatchers.We have in-depth explored the implementation of each module,and detailed introduction.Secondly,we propose an autonomous counter-based scheduling algorithm.This paper analyzes a greedy scheduling algorithm against starvation in detail,introduces its implementation principle,and points out that this algorithm has the disadvantages of high complexity and difficulty in application.On this basis,this article has carried on the optimization work,has redesigned the algorithm realization plan,obtained the new counter-based spontaneous memory scheduling algorithm.Thirdly,we completed the functional simulation test of the multi-channel DDR controller.The test results show that the multi-channel DDR controller model has the correct logic and complete functions,and the model accuracy reaches more than 85%,which is in line with project expectations.This paper validates and analyzes the performance of counter-based self-active scheduling algorithms.The verification results show that compared with the anti-starvation greedy scheduling algorithm,the algorithm greatly reduces the complexity and application difficulty of the algorithm,and reduces the extra resource overhead,but does not cause the performance to decrease.The experimental results show that the counter-based autonomous memory access scheduling algorithm has a significant improvement in the efficiency of memory access in the face of a large number of random access requests.