High-definition Television Chip Memory Controller Design

Nowadays HDTV chipsets are facing worldwide video and audio standards. So the memory used on the HDTV boards becomes larger in volume and faster in speed. This thesis is describing a memory controller which could be used in both on DDR2 and DDR3 memory. After such controller being implemented in a HDTV chipset, the controller is fully verified.In this thesis, the logic design is divided into two main parts: Arbiter and Controller. The main innovation points are as below:The arbiter is constructed following the Round-Robin arithmetic, and finished in the two-level architecture, which improves the efficiency. The Asynchronous FIFO bridges the arbiter and the controller. In that case the controller could work in an independent time domain to accommodate different speed memories. The Data width transaction adapts to memory bus. Both×32/×16 bits memories could work under these circumstances. The Address is stored in a{[ROW], [BANK], (and) [COLUMN]} format, accompanying with the pre-detection block, this mechanism could activate next operation bank in advance.Based on a huge amount of test, the thesis solve some below difficult problems:A set of ATE tests value and test flow are provided for better verifying result. These efforts could short ATE test term. A software method to measure bandwidth is presented. After trial runs and the arbiter ratio improve, the bandwidth efficiency improves from 54.48% to 59.17%, so the bandwidth is not the bottleneck any more in varies of applications.Finally the analog characteristic of signal integrity is measured. From the results, we can see that clock Jitter tJIT(CC) is between-143.28ps and 104.06ps while JEDEC spec is only between 160ps and 160ps. The timing of the stroke signal delaying to the clock signal tDQSS is between -126.2ps and 179.8ps, while JEDEC standard is between -375ps and 375ps. The minimum setup time tDS is 240ps, far larger than JEDEC standard 30ps.So there is assurance that the design product is successful.