The Research On Low-cost Self-Test Methods For 3D-SIC

TSV-based three-dimensional integrated circuit is an important direction of the development of IC. This technology has great advantages in shortening the length of interconnection, reducing power consumption, decreasing area overhead and allowing heterogeneous integration. However,3D IC is facing some challenges, such as heat dissipation, low yield and difficulty in test access et al. Aiming at solving the difficulty of test access, this dissertation mainly researches on how to complete 3D chip test through Built-in Self-Test and Built-off Self-Test. The main works are presented as follows:(1) Aiming at the problem of large area overhead of 3D BIST, this paper proposed a 3D BIST structure based on reconfigurable LFSR. This structure can be used in pre-bond, mid-bond and post-bond testing simultaneously, making the test resources of pre-bond testing can be reused for mid-bond and post-bond testing, thus the area overhead of mid-bond and post-bond testing shrinks greatly. In the design, the operation of merging test data for vectors and segments can reduce test time and test data storage volume. In order to further lower test cost, this paper improved the proposed test structure and gave a 3D structure based on variable-length seeds. Compared with Non-reconfigurable structure, experimental results demonstrated that the proposed reconfiguration method can reduce area overhead, test data volume and test time effectively at the same fault coverage, so the goal of reducing test cost is achieved.(2) A test data compression scheme based on position information coding is proposed in the dissertation, and the decompression structure of 2D and 3D are also given respectively. This scheme is based on test resource partitioning, and the main idea of it is generating the next stimuli by reversing some bits of the previous test response. So the test stimulus can be stored by storing the position information coding of reversed bits. In order to minimize the reversed bits and the code words, this paper first finds an approximate optimal solution according to Floyd-Warshall sorting algorithm before coding position information. Experimental results indicated that the proposed method can achieve higher test compression ratio.