Research On Built-in Self-test And Fault-tolerant Technology For Digital Reconfigurable Array

With the continuous development of the semiconductor technology and the integrated circuit, digital electronic system are more integrated, and its possibility of failure in the life cycle is even greater. Therefore, people gradually start to attach importance to the fault-tolerant ability in digital electronic system. The reconfigurable array has the characteristic of a repeatable programming, functional flexibility, high integration, short development cycle and low cost of research. The reconfigurable array has been widely used in the design of electronic system, It also provides a more flexible approach for fault-tolerant electronic system. Currently, self-test and fault-tolerant technology of reconfigurable array has become a research hot spot.This paper mainly studies the self-test and fault-tolerant technology of reconfigurable array, major research are as follows:(1) By improving the reconfigurable array, there are two operation modes: normal operation mode and self-test operation mode. When the reconfigurable array is in a higher degree of security conditions required, you can pull down test enable signal to make it work in self-test mode. It uses online circular self-test method, fault self-test doesn't affect the implementation of normal logic functions.(2) The reconfigurable array has the low utilization rate of resources and needs more time, this paper designed a two-level fault-tolerant method: 1) When the fault has been tested, first, using the spare BLE to achieve the first-level fault-tolerant, this process doesn't need the participation of build-in fault-tolerant processing unit; 2) When the cell unit lacks the spare BLE, by calling the build-in fault-tolerant processing unit to issue control commands, the nearest spare cell unit will replace the fault cell unit to achieve the second-level fault tolerance.(3) This paper exemplifies 6-bits parallel multiplier and 6-bits string out shift register, which are simulated and downloaded to FPGA board, to verify the fault-tolerant ability of reconfigurable array. By analysing and comparing with other reconfigurable arrays in fault-tolerant ability, resource utilization and fault tolerance time, the results show that the structure designed in this paper improves the resource utilization and reduces the time overhead.The work presented in this paper has been funded by National Natural Science Foundation of China (60871009) and Aeronautical Science Foundation of China (2009ZD52045).