Design Of A Reconfigurable Approximate DCT Circuit

With the development of multimedia services,video and images have become an indispensable part of people's lives.However,due to its large amount of data,the transmission of video and image information consumes a lot of power and shortens the battery life of mobile devices.To solve this problem,the image compression system is usually used to compress the data before image transmission,and the discrete cosine transform(DCT)is usually the core of this system.However,DCT is computation-intensive,and the direct implementation will occupy a lot of hardware resources,introduce a large power consumption,and affect the stability of the entire system.In order to simplify DCT operation,an reconfigurable approximate DCT circuit design is presented.Two kinds of approximate CSD coding schemes with different accuracy are designed by using the correlation between adjacent pixels of images,and the bit width is adjusted.Then,the approximate DCT architecture is obtained by using different degrees of approximation for different constant coefficient multiplications in DCT operation.In order to enable the circuit to work in different environments,combining with the energy compaction property of DCT,the reconfigurable design is added on the basis of the original architecture,so that the circuit has four working modes:normal mode,M1,M2and M3.By analyzing the complexity of the proposed DCT architecture,and ignoring the and gate in the reconfigurable design,43 adders/subtracters and 37 shifters are needed to complete the1-D DCT operation.Compared with the 64 adders and 46 shifters of the traditional DCT,the hardware cost is reduced by about 30%.The proposed DCT architecture is synthesized with 0.18um CMOS process,and its function simulation and performance simulation are carried out.The experimental results show that compared with the traditional DCT,the area of the proposed reconfigurable DCT in normal mode is reduced by 6.7%,and the power consumption is reduced by23.4%,but the PSNR only loses 1.6db.Compared with the circuit in different working modes,the accuracy of DCT in M1~M3 decreases in turn,but the power consumption of the circuit also decreases in turn.In the lowest accuracy mode m3,the PSNR of DCT circuit is reduced by 10.3db,and the power consumption is only 67.2%of the normal mode.Moreover,in all DCT architectures,the design in M3 has the lowest power consumption,but still achieves higher precision than some DCT circuits.Finally,the backend physical implementation of the proposed reconfigurable DCT design is carried out.The resulting layout has an area of 0.23mm~2 and a power consumption of 17.7mW.