Design Of Radio-Analog Front End For Passive UHF RFID Tag With Accelerometer

RFID (Radio Frequency Identification) has the characteristics of small volume, low power consumption, no contact information transmission and so on. And it is widely used in intelligent recognition, positioning, monitoring, remote automatic testing and so on by combining with various kinds of sensors. This thesis studies the radio-analog front-end of the UHF(ultra-high frequency) RFID with the accelerometer.The main work of this thesis includes the following aspects:1. According to the ISO18000-6 Type C protocol specification, this thesis will study the system structure of the passive UHF RFID with accelerometer, and determine the electrical performance parameters of every sub-module.2. This thesis will study the design of the accelerometer and introduce the operating principle of the accelerometer and the positive processing technology of bulk silicon based on Deep Reactive Ion Etching.3. This thesis will design the radio-analog front-end circuit of the passive UHF RFID tag integrated accelerometer on SMIC 0.18um CMOS technology., which is consisted of a rectifier, a voltage reference, a voltage regulator and protection circuit, a power on reset circuit, a demodulator circuit, a modulator circuit, a clock circuit, an interface circuit of accelerometer. For the purpose of low power consumption, the rectifier offers 1.8V output voltage for the POR and digital baseband and 1.0V for the other analog circuit. By using subthreshold MOS transistor to reduce power consumption in the reference voltage generation circuit. RFID tag output uses the backscattered working mechanism of the ASK modulated which adjusts the matching degree of the input impedance to the tag antenna,it can make the antenna back radiation of the carrier signal, then send the tag’s output to the reader, which avoid the active emission of radio-frequency carrier, besides, it is very low power consumption. The simulation results show that the radio-analog front-end system can work properly with the preceding date rate 40Kbps to 160Kbps, and the total power consumption is about 7uW, so it satisfies the low power design specifications.