Research On RF And Analog Front End Of Low Power Passive UHF RFID Tag Chip

Ultra high frequency radio frequency identification (UHF RFID) technology,that identify information by emitting , receiving and proceeding the radio frequency(RF) signals which carry the data and energy, has been widely used in the logistics and intelligence traffic system and so on.The RF analog front end of passive tag in the UHF RFID system was proposed in this paper. The energy over the tag comes from the RF signals emitted by the reader. Receiving and reflecting RF signals in radar principle, the RFID tag absorbs energy inversely proportional to the square of the distance, that is to say, the longer distance between the tag and the reader, the lower power destiny that the tag can receive. So, the dissipation is the key to limit the working range of the RFID. The paper resolved this problem by improving the energy utilization rate via increasing absorption and decreasing dissipation.In the first, based on the ISO/IEC 18000-6 Type C protocols, this paper gives an exposition of the working link and the basic principle of RFID system, and specifies the requirement and the target on carrier frequency and data modulation that the protocols stipulate. These work offered the theoretical foundation and reference for the design of receiver and modulation-demodulation module. The second, the part to accomplish impedance matching between antenna and tag chip in the RF front end was studied to maximize the energy transmitted to tag; sub threshold technology was utilized in analog front end to reduce the quiescent current of every analog module to decrease dissipation, as the current flowing through every branch circuit is at nanoampere range and the MOSFETs work in the sub threshold region. At last, layout and post-simulation were accomplished with Chartered semiconductor 0.35μm RF CMOS process. The whole area of RF analog front end chip is 0.8mm~2, the quiescent current is less than 10μA. The simulation results indicate that every module of the chip stably works and the requirement of the design target is achieved in all situation of meeting the protocol requirements.