Design Of A Passive HF RFID Analog Front End Circuit Based On 0.18um Technology

Radio frequency identification technology (RFID) is a non-contact automatic identification technology that involves high-frequency technology, electromagnetic coupling technology, semiconductor technology, cryptography, communications and other disciplines. For its convenience and safety, RFID has been widely applied to traffic management, access control systems, logistics management, automation and other fields.This paper focuses on the design of analog front-end circuits in electronic tag. The design belongs to high-frequency passive radio frequency identification technology (HF RFID), which is based on ISO/IEC14443 type-A protocol with operating frequency of 13.56MHz. This paper mainly elaborates on two aspects:First, the theoretical basis and design implementation of analog front-end circuits; Second, circuit simulation and layout design of these circuits. There are two characteristics, this design uses low dropout regulator as a voltage regulator circuit, and adopts a clock recovery circuit based on phase-locked loop, effectively reducing the cost of the chip and improving the stability of the chip communication.Analog front-end circuit of electronic tag consists of the following parts:antenna limiter circuit, rectifier circuit, voltage regulator circuit, clock recovery circuit, reset circuit, modulation circuit and demodulation circuit. The antenna limiter circuit provides an upper limit for input signal to prevent post-stage circuit from being destroyed due to excessive voltage; rectifier circuit and voltage regulator circuit provide the DC power supply for the passive chip so as to ensure the tag has adequate and stable supply; clock recovery circuit can recover the carrier wave from the reader, and then provides a clock signal to digital circuit after the handling of back-stage circuit; reset circuit can provide a power-on reset signal to the digital circuit and set an initial state for the digital circuit in order to avoid the occurrence of logical confusion when the digital circuit is operating. Modulation circuit uses load modulation mode and demodulation circuit employs envelope detection mode.The entire analog front-end circuit is designed by adopting SMIC 0.18μm EEPROM technology. The electronic tag can acquire magnetic field strength in the range from 1.5A/m to 7.5A/m through building the reader model. The circuit is simulated by Spectre and the backend layout is designed Virtuoso. The DRC and LVS are done by Calibre.The simulation results indicate that the analog front-end circuit designed by this paper works perfectly and it can meet the requirements of the protocol. Power consumption of the entire analog front-end circuit is less than 100μW, the area of the layout is 650μm×450μm, thus the circuit has such advantages as low power consumption, low cost and high reliability.