Study Of Analog Front End And EEPROM Of Low Power Passive UHF RFID Tag

RFID (Radio Frequency Identification) technology is a wireless automatic identification technology. The principle is the automatic identification of an object by radio-frequency signal. The process does not require human intervention to identify work, and is considered to be a wireless version of the barcode.RFID is an important part of Internet of Things. With a variety of new life philosophy and technology concept generation, it will surely be developed rapidly. Over the past few years, wireless UHF identification systems (UHF RFID) technology is being rapidly applied, especially in the supply chain, true and false identification, vehicle tracking, product tracking and other areas of widespread concern. Meanwhile, as to an important part of the electronic tag, embedded EEPROM has been also widely used in these areas, and focuses on the design of innovation.This paper focuses on the passive UHF RFID tag chip analog front end and EEPROM memory design. At the beginning of the paper, the paper discusses the principles of RFID systems as well as its overall architecture of RFID system works. Thereafter, the system structure UHF passive UHF RFID tag chip was designed. The paper studied the low-power passive RFID chip design related to the key technical difficulties. First, the paper presents a study of low-power analog front-end demodulation circuit. Compared with the conventional demodulation circuit the circuit structure is simple, fast data demodulation. Next, the paper designs a memory control timing circuit. This circuit can control the memory circuit from reader issuing commands and data to completing flash memory or a read operation. Compared with the storage principle controlled by traditional architecture electronic tags, circuit reduces the number of the circuits of analog front end portion and electronic label digital circuits in working condition. Thereby reducing the overall power consumption of the electronic tag during flash operation. Meanwhile, the memory can work completely independent of external circuit. This prevents the effects on memory work processes cause of unexpected interruption of communication during flash operation. In addition, the paper proposes an improved storage array structure. It can overcome the shortcomings of traditional storage structures that erase and write operations must be carried out separately. Improved memory array circuit can be achieved erase and write operation simultaneously. And the circuit can reduce power dissipation. Each workflow will halve working hours, thereby shortening working time of electronic tags. Paper designed a test and development platform for passive UHF RFID tag chip. Authentication-related functionality can be done. The platform can be tested directly communicate with the reader, and can also be connected with an external FPGA for testing. Thesis research on the design of passive UHF RFID tag chip front-end analog circuitry and EEPROM memory circuit system structure transformation. Among them.This project uses the process flow sheet for0.18μm2P4M EEPROM communication protocol for ISO/IEC18000-6standard. Circuit design for the UHF RFID tag has low power high performance characteristics. Final test results show that the designed circuit reduces the UHF RFID tag chip overall power consumption.