Reseach For System Level Design Of PLL Frequency Synthesizer

Frequency synthesizer is one of the most crucial parts in electronic communication system, it plays an important role in clock signal generating and local oscillating signal generating. Among frequency synthesizers’ implementations, PLL based frequency synthesizer is the mainstream and widely studied. Nowadays, the most widely used system structure of PLL based frequency synthesizer is charge-pump PLL, it contains digital circuit modules and analog circuit modules, and it’s a mixed analog-digital feedback system. With respect to this complicated control system, system structure design is the prerequisite to make a well designed PLL, and the setup of system level parameters is the crucial part to make a good performance synthesizer.In this dissertation, signal transmission theories of PLL system is firstly studied and analyzed, based on these theories, system level modeling about PLL is studied, both behavioral level model and circuit module level model are studied, the main tools for this two modeling is MATLAB and Simulink. Then study about phase noise of PLL is carried out, PLL phase noise simulation, modeling and optimization are implemented. Based on the study about macroparameters of system level, detail integrated circuits of main blocks is studied, to make sure that each functional block satisfies system’s requirement and get the optimized design result.Base on the study and analysis of theories above, a PLL based frequency synthesizer with the frequency range of 400 MHz~450 MHz is designed. With reference to the system design theories, firstly, detail parameters of each functional block are calculated and optimized depending on the system requirements. Then doing pre-simulation based on 180 nm RF process with Cadence spectre. The layout is designed depending on the well designed pre-simulation result with Virtuoso software. Then the chip is taped out on 180 nm RF process. After manufacture and packaging, PCB is designed for testing. The chips parameters is as following: operating voltage 1.8 V, power consumption is below 15 m W, frequency range is 400 MHz~450 MHz, frequency step is 15 MHz, bandwidth is 200 KHz,locked time less than 20 μs, the average phase noise is-118 d Bc/Hz@1 MHz, the total area is 1620 μm×1350 μm.