Research On Key Techniques Of UWB Phase Locked Loop Frequency Synthesizer

In recent years,the rapid development of wireless communication has caused more and more researchers to pay attention to wireless communication technology.Phase-locked loop frequency synthesizer is a key module used to provide local oscillator signals in wireless transceivers.Its performance affects the performance of wireless transceivers.Design specifications such as a wide frequency range,low phase noise,and low power consumption are proposed for the phase-locked loop frequency synthesizer,in order to meet the ever-increasing performance requirements of wireless transceivers for low power consumption,high integration,and low cost.Therefore,the research and design of this paper focuses on the system of the phase-locked loop frequency synthesizer and its key modules.This paper first analyzes the structure and key parameters of the phase-locked loop frequency synthesizer,establishes an S-domain linear time-invariant system(LTI) model,and analyzes the loop stability.Various noise sources in the phase-locked loop frequency synthesizer are pointed out,and the contribution of these noise sources to the total phase noise is obtained by deriving the phase noise transfer function.After that,two implementation methods of frequency division of 1.5 and multi-VCO are introduced,and their advantages and disadvantages are analyzed.The voltage-controlled oscillator is a key module to achieve frequency output,so the voltage-controlled oscillator is designed next: First,the basic principle of the traditional inductor-capacitor oscillator is introduced,and the phase noise is analyzed and derived,but this The phase noise performance of this type of oscillator is not as good as a Class C VCO.In the further analysis of the C-type VCO,it is found that it is difficult to balance the reliability of the oscillation and the high current efficiency.Therefore,in this design,a Class C VCO with dynamic offset is used to solve this problem,and a current steering array is added to improve the performance stability under PVT changes.After the design is completed,the performance parameters of the dual VCO are simulated and verified,and the overall layout of the VCO is designed.After that,other modules in the phase-locked loop frequency synthesizer loop are designed and analyzed.The frequency divider consists of a pre-frequency divider and a programmable frequency divider.This article analyzes their working principles and designs the circuit structure.In the design of the Phase Frequency Detector,in order to avoid the generation of the phase detector dead zone in each process corner,a programmable delay control module is used.In the design of the charge pump,the basic principle and non-ideal effects of the charge pump are introduced first,and several common charge pump structures are given,and their advantages and disadvantages are analyzed.Finally,combining the advantages of different types of charge pumps,an optimized programmable charge pump is given.In the design of the automatic frequency calibration module,the working principle and algorithm are analyzed and designed.Finally,based on the TSMC 65 nm process,the aspects that need attention in layout design are introduced,and the circuit layout design is carried out.Finally,the layout area of the phase-locked loop frequency synthesizer is 1.5mm × 1.5mm.In the post-imitation,the center frequency of the phase-locked loop frequency synthesizer is 13 GHz,the frequency coverage ranges from 8.4 to 17.6 GHz,and the lock time is less than 25 us.Below-111.1 dBc/Hz @ 1MHz.