The Design And Implementation Of Bus Architecture Of Integrated Information Processing Platform

In the future, information warfare will be the coordinated battle of aerospace, heaven and earth together. Integrated information processing platform, as universal airborn aviation elctromechanical system of integrated aircraft, needs support reconstruction of hardware and software to carry multi-functional multitask, such as probe, interference reconnaissance and communications. It put forward higher requirements for the performance of the platform, such as data processing capability. The performance of bus system has a decisive influence on the overall performace of avionics system. Date transfer rate is the most critical performance indicators of avionics bus. Integrated information processing platform requires that the bus system should provide 1000Mb/s-level high-speed internet for modules inside, and provide 100Mb/s-level high-speed interconnect between subsystmes. It also requires a bus system with high reliability, high real-time, low cost and so on. Traditional avitation bus such as ARINC429, MIL-STD-1553 B, VME, can not meet its performance requirements for transmission. so it is necessary to design a new bus system for integrated information processing platform.Based on the laboratory project of unmanned aerial vehicles information system integration technology reseachment, this thesis design and implement the bus system of integrated information processing platform. First of all, based on the design objective and principle of reliable, real-time as well as economical, the thesis formulate the overall scheme of two-level compounded bus system architecture, in which internal bus Open VPX provide 1000Mb/s interconnect for modules inside subsystems and external bus AFDX provide 100Mb/s interconnect for subsystems. Then the thesis design detailed dual redundant bus topology of Open VPX and AFDX. Wherein the design of Open VPX bus topology is an innovation based on the existing specifications. The innovations include adding expansion plane, to provide support for high-speed data stream processing; Splitting switch management slot into two slots, to balance the contradictions of excessive number of interfaces and limited volume; adding data path redundancy based on functional redundancy to further enhance the reliability. Next the thesis implements main hardware module of the bus system, including Open VPX backplane, bus system control board, VPX switch board and so on. Driver is the interface for application to call the bus function. so next, on the bassis of hardware circuit, The thesis implements the bus driver based on Vx Works operating system and P2041 processor using hierarchical software design thought, including implements the AFDX board driver and SATA controller driver. In order to improve the real-time performace of the system, these drivers implement the data transceiver using event triggerd interrupts and DMA techonology.Finally, the thesis tests the realization of the bus system. First of all, load the MCU initialization program, reset configuration and system image to boot the bus system control board successful. Then write the data transmission application to test the data transmission rate of Open VPX and AFDX. Finally, test the overall performace of the bus sytem. The experimental results show that the performance of the bus system achievies the design goal.