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Design And Implementation Of High Performance Radar Real-time Signal Processing System Based On OpenVPX

Posted on:2016-07-30Degree:MasterType:Thesis
Country:ChinaCandidate:Y FengFull Text:PDF
GTID:2298330452464927Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
With the development of the new radar system and introduction of some new radarconception such as software radar, Radar signal processing system requires a highersampling frequency, the higher data transfer bandwidth and faster data processing speed.Also, because of the specific application environment, it puts forward more demandingneeds with earthquake resistance, heat resistance, function reliability. So, how to build ahigh speed embedded real-time radar signal processing system on the basis of the theory ofparallel processing and the features of radar signal processing system has become a key toimproving the performance of radar systems.Firstly, this paper studies development and application status of system architecture,embedded processors, embedded interconnect bus within an embedded high-performanceparallel processing system. Then we find out the platform architecture, the processors andinterconnect bus which are suitable for radar signal processing system. Based on theanalysis of embedded processing system performance evaluation method, we get the keyfactors influencing the performance of parallel processing system, which is the theoreticalbasis to build a high-performance real-time radar signal processing system.Then, based on research of embedded high-performance parallel processing system,combining the characteristics of radar signal processing system, select the industry’sadvanced OpenVPX platform architecture, we proposed a standardized, universal, modular,scalable system, analyze the system node model and then proposed distributed storageheterogeneous processing node model and common I/O node mode, and analyze theimplementation of SRIO and PCIE. With SRIO this paper studied flexible configuration ofSRIO switch routing to achieve high-speed non-blocking data transmission andsynchronization mechanism of SRIO network. With PCIE this paper studied the keytechnology of synchronization initialization mechanism of PCIE network to achieve asuccessful multi-device enumeration and the implementation of non-Spread Spectrum clockof PCIE.Finally, on the basis of distributed storage heterogeneous processing nodes module, thispaper designed two high-performance parallel processing cards with TI’s TMS320C6678DSP and domestic BWDSP100DSP respectively. Introduction of SI and PI design methodto ensure correct circuit design of large-capacity data storage, high-speed businterconnection, complexity power distribution.Then this paper analysis bandwidthmatching between processing, storage, transmission in order to maximize the parallel processing performance. It is verified that the cards have powerful parallel processingperformance and proposed high-performance radar real-time signal parallel processingsystems based on OpenVPX has the module、universal and scalability advantages.
Keywords/Search Tags:Embedded System, Parallel Processing, OpenVPX, SRIO, PCIE, TMS320C6678, BWDSP100
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