Keep The Power Consumption Of Edram Design, Based On The Gain Of The Unit's High-speed Low-data-

In this paper, the history of DRAM's development is introduced and the performance index of embedded memory is proposed. According to embedded application, an reformed 2T gain cell structure featured logic technology, improved read speed and extended data retention is acquired by the analyse and comparision of several kinds of DRAM cells. The array structure and periphery circuits which perform basic read and write operation is given. Meanwhile, a test chip is designed based on high speed read write scheme and compact charge transfer refresh scheme to achieve the requirements of speed and power of embedded memory. With 6 ns clock cycle, the simulation results illustrate that the write cycle of memory is 3 ns and is reduced 23%,meanwhile the access time is 1.8 ns and is reduced 15% compared with conventional scheme. Under refresh mode,SA power consumption and refresh time is reduced 58% and 43% respectively compared with conventional scheme.