Design Of Speculative Read-write Circuit For Spin Magnetic Memory

Under the background that semiconductor technology is constantly approaching physical limits,various new memory technologies are driving the innovation and development of integrated circuits.STT-MRAM has the advantages of high access speed,easy hybrid integration and high durability,which make it a major competitor of next-generation memory.However,the disadvantages of asymmetric writing and random conversion in STT-MRAM cause low access success rate of STT-MRAM and the writing power/delay loss to be inconsistent with design expectations.Charge share,high margin(CSHM)SA circuit with charge sharing and cross feedback mechanisms is proposed firstly to improve SA read sensing margin.Besides,timing speculation technology to STT-MRAM is implemented to adjust the bit error rate to adapt to different scenarios through two write operations for the first time,which reduces the high write power consumption and delay of STT-MRAM.And a timing speculation combined with approximate storage technology is applied in image processing.Finally,a finite field compression technique based on cross-detection SA is proposed to reduce the application cost of ECC in area and power consumption.Using SMIC 14 nm Fin FET process,the proposed CSHM-SA shows improved read yield than previous SA implementations by more than 9%.With SMIC 28 nm process,the delay and power consumption of the timing speculative writing technology are reduced to 56.25% and56.18% respectively,compared with the traditional writing scheme.The design of the ECC 2BIT with a capacity of 2048×44 MRAM was completed and the area and power consumption of proposed ECC scheme is decreased by more than 20% and 25% respectively.The technologies proposed in this paper which aimed to low writing power consumption/delay and high reliability have been implemented by simulation and specific IP,and can be applied to image processing,voice recognition and other fields.