Research On The Diagnosis And Fault-tolerant Technology Of The Faults On Part Of Key Links For NoC

3D NOC is the high combining of 3D technology and Network-on-Chip, possess of the advantages of 3D IC and NoC, such as, high scalability, high integration, low power consumption, and low delay. All communication nodes and resource nodes are connected into a huge network by interconnect wires. The interconnect wires include common data links of routers and routers, links of routers and IP cores, and TSV in vertical direction of the chips. A special interconnect wires is the bypass of IEEE 1500 test wrapper. It may lead failure in the process of manufacturing and using because of immature process. In order to ensure the normal communication of 3D NOC chip, this thesis is aimed at diagnosing and fault-tolerance for two key data links.In order to solve the problem of communication in 3D NoC, the problem of TSV failure and interconnection wires short-circuit, etc., the interconnection wires in the network need to be tested. The technology for testing of 3D IC has become constraints of design and manufacture in 3D chip. How to avoid the problem of reliability of complex structure for testing TSV, and ensure the correctness have become key problems. A new test structure using rebound mechanism is presented in this thesis. Add some hardware mechanism for test TSV in the upper and lower of chips to detect defect of TSV. Then use a redundant TSV to tolerant the fault. The proposed architecture does not need complex hardware and frequent interaction in two layers. We use DC simulation tools to evaluate the area cost and pspice to evaluate the power consumption of the proposed architecture. Experimental results show that this test structure requires small area cost and low power consumption.The IEEE 1500 standard structure provide a test wrapper to test routers and a bypass to shield faulty routers. However, if a bypass fails, not only we can not use it to tolerant fault, but also it will disturb other test responses in the same scan chain. To solve the problem, we propose a diagnostic method for bypass fault in routers’test wrapper in NoC. We use the Depth-first shortest path to get the shortest path from the scan-in port to the scan-out port, and we separate routers by using recursive partitioning stepwise refinement to construct multiple scan test chains. So the localization of bypass fault could be realized. Then we also propose a structure to tolerate the bypass fault. Experiment result shows that the proposed approach and architecture can effectively diagnose bypass fault of test wrapper, increase the reliability of the NoC test, and improve the yield of chip.