SOPC Based Control Module And IP Core Design Technology Research

Video surveillance, aerospace, medical devices, automotive and other fields often need control module to have the functions of system management, system monitoring, real-time data processing. With the rapid development of embedded system applications, the control module is required to have advantages of high-performance, multi-function, miniaturization, flexibility, real-time and lower power consumption. Commonly used control module with processor and peripheral architecture has disadvantages of low-leveled combination, big hardware structure, non-flexibility, high costed interaction between software and hardware. SOPC(System-on-a-Programmable-chip) is a recently developed system-level programmable chip technology, which has the advantages of high integration, flexibility, collaboration between software and hardware. To fulfill the need for application of the new control module, the thesis investigates the control module nad IP core designing technology based on SOPC in the development of high-performance embedded platform, which can flexibly and efficiently implement complex embedded system control module applications.The main work of the thesis is as follows:(1) to fulfill the function and demand of high-performance embedded development platform, the thesis proposed a system design scheme based SOPC chip; (2) to fulfill the need of software and hardware interaction, the thesis analyzed the characteristics of SOPC platform, studied the processor and FPGA interconnect solutions based on SOPC and presented a general FPGA framework based on dual interconnect structure; (3) to realize the specific need for processing the stream data, the author designed IP core interconnect structure based on AXI4-Stream protocol, and proposed DDR cache module programme with the feature of big throughput capacity, multi-level cache, simultaneous reading and writing, Pipeline working; (4) to fulfill the requirement for the board interconnection, the thesis investigated the board interconnection scheme, using hardware and software collaboratively to achieve the data transfer function between RapidIO endpoints based on user-defined protocol; (5) the thesis proposed the design and implemented the function of the partial dynamic reconfiguration of three-way CAN/RS-422 channel and CPU interface module IP core.Through experiment and the test of actual platform, the results show the control module based on dual interconnect structure of the high-performance embedded system can achieve the functionality of system control, data transmission, data caching, dynamic reconfiguration. DDR cache module able to read and write simultaneous, work in pipeline mode; three-way CAN/RS-422 channel achieved the ability of partial dynamic reconfiguration; the transmission rate based on RapidIO protocol and DMA channel is about 327MB/s, reach 63.2% of the theoretical bandwidth.