| Due to the fast-developing technology of embedded system and communication network, there is a critical need for high-speed interconnect technology. While traditional data buses can’t meet the demand of high-speed transmission, there emerges the RapidIO technology, whose typical characteristics are high-bandwidth, high reliability, low-latency, small number of pins and flexible structure, providing an good solution to the high-speed data transmission in embedded system.The work done in this thesis about RapidIO is as follows1.Study and analysis of the RapidIO specification 2.1:Analysis of the RapidIO specification is done by introducing the methods and means during the core design and implementation. The three-layer architectural hierarchy, which are logical layer transport layer and physical layer,and their functions are discussed. Transaction and operation types, execution of operations, formats of packets containing these transactions are illustrated.Control symbols, which are used in flow control, packet delimitation and error management, are explained.2.The implementation of RapidIO 2.1 specification:On the basis of studying RapidIO specification, an RTL level IP core of serial RapidIO of 1x/4x mode is designed using Verilog Hardware Description Language. The core includes logical transmitting and receiving modules transmitting and receiving buffer modules and a serial physical layer module.In this design,the serial physical module is divided into a serial protocol layer module, a physical coding sublayer(PCS) module and a physical medium attachment(PMA) module. The RTL schematic after synthesis of all these modules are presented with their functions and signal ports detailedly explained. Then the verification results of each module are also presented.3.Verification of the IP core:The core,as a whole, is linked to commercial RapidIO cores of Xilinx to verify it can act as specification’s description. Specifically, the commonly used operations of read (NREAD),write(NWRITE),write_with_response(NWRITE_R), streaming_write(SWRITE) and local and remote maintenance read/write(MAINTENANCE READ/MAINTENANCE WRITE) defined in protocol are tested when the core works as both a host and a slave. From the results of verification, it is known that the core can initiate request transactions and deal with the transactions sent by its partner correctly and the high-speed channel of transmitting and receiving data is built successfully.Judged from the simulating results of the core linking to a mature industrial IP core, the core is considered be able to implement basic operations defined by the specification and its performance achieves the desired aims, which could be a foundation for further developing and application of high-speed serial communication interfaces in embedded systems chips. |
