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The Design Of High-speed Data Transmission System Based On RapidIO

Posted on:2014-03-04Degree:MasterType:Thesis
Country:ChinaCandidate:L LiuFull Text:PDF
GTID:2268330425966243Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
With the development of the underwater acoustic technology, engineering practical levelenhanced unceasingly, more and more data was transported in the communication. This thesisfocused on the problem which large amount of data was transported at a high speed inreal-time on vector array positioning system platform.A set of high-speed data transmissionsystem which based on RapidIO protocol was built in this paper, the system was composed oftwo pieces of Cyclone IV processor platforms and a RapidIO switch platform which based onTsi578platform.The Cyclone IV FPGA processing platform and the switch platform which was based onTsi578hardware’s principle diagram and PCB design and debugging were completed in thispaper.Cyclone IV FPGA processing platform included the design of configuration circuitry,power circuit, clock circuit and interface circuit.The switch platform included the followingsections:the design of switch chip circuit, the clock circuit, power module circuit and theconfiguration circuit, reset circuit, interface circuit and connect circuit. Due to the transferrate of RapidIO was1.25Gbps, a high-speed PCB was designed to the switch platform PCBboard, which included traces of the RapidIO differential line, the number of decouplingcapacitors and distribution, laminated design, impedance matching.Then the RapidIOhigh-speed transmission system network architecture was designed, it included the RapidIOhigh-speed transmission system in the network topology, RapidIO protocol in detail and theRapidIO was realized in SOPC (system on programmable chip). A simulation was done toRapidIO application model. Firstly, RapidIO application model was established, then thesimulation results was obtained. Because the pre-processed data of the system was in parallel,so the data was changed from parallel to serial. Finally, the functional testing was done to thedata transmission network, the logical unit number and the size of the memory whichconsumed in FPGA was got, and measuring the rate of transmission scheme was presented.
Keywords/Search Tags:High-speed, RapidIO, FPGA, SOPC
PDF Full Text Request
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