Design And Implementation Of Serial RapidIO Interface Based On FPGA

With the continuous improvement of embedded processors' performance,it is hard for the traditional parallel bus to satisfy the increasing requirement of bandwidth in embedded systems.Due to its high speed,low cost and low pin count characteristics,Rapid IO interconnection techonology has replaced the traditional parallel bus and it can meet the wide demand of high-performance embedded systems.As the only authorized international standard in embedded field,RapidIO interconnection technology is also the best solution for high performance embedded interconnection in future.At present,most of the world's mainstream embedded manufacturers have already supported the Rapid IO interconnection standard,and launched a variety of Rapid IO-based products,including development tools,embedded systems,IPs,softwares,test equipments,semiconductor products and so on.Based on the study carried out in this thesis on the RapidIO interconnection protocol and some technical documents of related products,a serial interconnection interface based on RapidIO protocol has been designed and implemented.The interface realizes several fundamental functions,including the packing and unpacking of the packets,the orderly transmission and reception of the packets,the initialization process,the receivercontrolled flow control and so on.Firstly,this thesis introduces the research background of RapidIO interconnection technology and the development status at home and abroad.Then,the hierarchical architecture,typical operation flow,common operation type,format of various data units and reliability mechanism of RapidIO interconnection protocol are analyzed in depth.What's more,the fundamental functions of the serial link part in protocol are extracted as needed,and the overall design scheme of the serial RapidIO interface circuit is presented.According to the design idea of Top-Down and the modular design method,Verilog Hardware Description Language is used to realize most functional modules,including the packing logic,the unpacking logic,the logical layer scheduling logic,the initialization state machine,the sending channel,the receiving channel and the retransmission recovery state machine.To lower the difficulty of the design,the high-speed serial transceiver cirtuit is implemented using Rocket IO IP core of Xilinx's FPGA.In addition,the clock domain division and clock allocation of the circuit are analyzed,and cross-clock domain handling is carried out on the asynchronous signal interaction.Finally,the simulation platform is built based on Modelsim software.Respectively,module-level simulation and overall simulation of the serial RapidIO interface circuit are carried out.After FPGA verification,the test results show that the serial RapidIO interface circuit demonstrated in this thesis functions well.